NXP Semiconductors LPC1768 User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 610 of 841
NXP Semiconductors
UM10360
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
31.6.2.1 Peripheral-to-memory or memory-to-peripheral DMA flow
For a peripheral-to-memory or memory-to-peripheral DMA flow, the following sequence
occurs:
1. Program and enable the DMA channel.
2. Wait for a DMA request.
3. The DMA Controller starts transferring data when:
– The DMA request goes active.
– The DMA stream has the highest pending priority.
– The DMA Controller is the bus master of the AHB bus.
4. If an error occurs while transferring the data, an error interrupt is generated and
disables the DMA stream, and the flow sequence ends.
5. Decrement the transfer count.
6. If the transfer has completed (indicated by the transfer count reaching 0):
– The DMA Controller responds with a DMA acknowledge.
– The terminal count interrupt is generated (this interrupt can be masked).
– If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr,
DMACCxDestAddr, DMACCxLLI, and DMACCxControl registers and go to back to
step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow
sequence ends.
31.6.2.2 Peripheral-to-peripheral DMA flow
For a peripheral-to-peripheral DMA flow, the following sequence occurs:
1. Program and enable the DMA channel.
2. Wait for a source DMA request.
3. The DMA Controller starts transferring data when:
– The DMA request goes active.
– The DMA stream has the highest pending priority.
– The DMA Controller is the bus master of the AHB bus.
4. If an error occurs while transferring the data an error interrupt is generated, the DMA
stream is disabled, and the flow sequence ends.
5. Decrement the transfer count.
6. If the transfer has completed (indicated by the transfer count reaching 0):
– The DMA Controller responds with a DMA acknowledge to the source peripheral.
– Further source DMA requests are ignored.
Table 566. DMA request signal usage
Transfer direction Request generator Flow controller
Memory-to-peripheral Peripheral DMA Controller
Peripheral-to-memory Peripheral DMA Controller
Memory-to-memory DMA Controller DMA Controller
Source peripheral to destination peripheral Source peripheral and destination peripheral DMA Controller

NXP Semiconductors LPC1768 Specifications

General

Brand	NXP Semiconductors
Model	LPC1768
Category	Microcontrollers
Language	English