UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 182 of 841
NXP Semiconductors
UM10360
Chapter 10: LPC176x/5x Ethernet
to a fragment of a frame. By using fragments, scatter/gather DMA can be done: transmit
frames are gathered from multiple fragments in memory and receive frames can be
scattered to multiple fragments in memory.
By stringing together fragments it is possible to create large frames from small memory
areas. Another use of fragments is to be able to locate a frame header and frame payload
in different places and to concatenate them without copy operations in the device driver.
For transmissions, the Last bit in the descriptor Control field indicates if the fragment is the
last in a frame; for receive frames, the LastFrag bit in the StatusInfo field of the status
words indicates if the fragment is the last in the frame. If the Last(Frag) bit is 0 the next
descriptor belongs to the same Ethernet frame, If the Last(Frag) bit is 1 the next descriptor
is a new Ethernet frame.
10.17.2 Initialization
After reset, the Ethernet software driver needs to initialize the Ethernet block. During
initialization the software needs to:
• Remove the soft reset condition from the MAC
• Configure the PHY via the MIIM interface of the MAC.
Remark: it is important to configure the PHY and insure that reference clocks
(ENET_REF_CLK signal in RMII mode, or both ENET_RX_CLK and ENET_TX_CLK
signals in MII mode) are present at the external pins and connected to the EMAC
module (selecting the appropriate pins using the PINSEL registers) prior to continuing
with Ethernet configuration. Otherwise the CPU can become locked and no further
functionality will be possible. This will cause JTAG lose communication with the target,
if debug mode is being used.
• Select RMII mode
• Configure the transmit and receive DMA engines, including the descriptor arrays
• Configure the host registers (MAC1,MAC2 etc.) in the MAC
• Enable the receive and transmit data paths
Depending on the PHY, the software needs to initialize registers in the PHY via the MII
Management interface. The software can read and write PHY registers by programming
the MCFG, MCMD, MADR registers of the MAC. Write data should be written to the
MWTD register; read data and status information can be read from the MRDD and MIND
registers.
The Ethernet block supports RMII PHYs. During initialization software must select RMII
mode by programming the Command register.
Before switching to RMII mode the default soft reset (MAC1 register bit 15) has to be
de-asserted. The phy_ref_clk must be running and internally connected during this
operation.
Transmit and receive DMA engines should be initialized by the device driver by allocating
the descriptor and status arrays in memory. Transmit and receive functions have their own
dedicated descriptor and status arrays. The base addresses of these arrays need to be
programmed in the TxDescriptor/TxStatus and RxDescriptor/RxStatus registers. The
number of descriptors in an array matches the number of statuses in an array.
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