UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 583 of 841
30.1 Basic configuration
The DAC is configured using the following registers:
1. Power: The DAC is always connected to V
DDA
. Register access is determined by
PINSEL and PINMODE settings (see below).
2. Clock: In the PCLKSEL0 register (Table 40
), select PCLK_DAC.
3. Pins: Enable the DAC pin through the PINSEL registers. Select pin mode for port pin
with DAC through the PINMODE registers (Section 8.5
). This must be done before
accessing any DAC registers.
4. DMA: The DAC can be connected to the GPDMA controller (see Section 30.4.2
). For
GPDMA connections, see Table 543
.
30.2 Features
• 10-bit digital to analog converter
• Resistor string architecture
• Buffered output
• Selectable speed vs. power
• Maximum update rate of 1 MHz.
30.3 Pin description
Table 537 gives a brief summary of each of DAC related pins.
UM10360
Chapter 30: LPC176x/5x Digital-to-Analog Converter (DAC)
Rev. 3 — 19 December 2013 User manual
Table 537. D/A Pin Description
Pin Type Description
AOUT Output Analog Output. After the selected settling time after the DACR is written with a new value,
the voltage on this pin (with respect to V
SSA
) is VALUE ï‚´ ((V
REFP
- V
REFN
)/1024) + V
REFN
.
Remark: The DAC output is disabled when the device is in deep-sleep, power-down, or deep
power-down mode.
V
REFP
, V
REFN
Reference Voltage References. These pins provide a voltage reference level for the ADC and DAC.
Note: V
REFP
should be tied to VDD(3V3) and V
REFN
should be tied to V
SS
if the ADC and
DAC are not used.
V
DDA
, V
SSA
Power Analog Power and Ground. These should typically be the same voltages as V
DD
and V
SS
,
but should be isolated to minimize noise and error. Note: VDDA should be tied to VDD(3V3)
and VSSA should be tied to VSS if the ADC and DAC are not used.
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