NXP Semiconductors LPC1768 - System Handler Priority Register 1; System Handler Priority Register 2; System Handler Priority Register 3; System Handler Control and State Register

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User manual Rev. 3 — 20 December 2013 776 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
Each PRI_N field is 8 bits wide, but the processor implements only bits[7:3] of each field,
and bits[2:0] read as zero and ignore writes.
34.4.3.9.1 System Handler Priority Register 1
The bit assignments are shown in Table 664
.
34.4.3.9.2 System Handler Priority Register 2
The bit assignments are shown in Table 665
.
34.4.3.9.3 System Handler Priority Register 3
The bit assignments are shown in Table 666
.
34.4.3.10 System Handler Control and State Register
The SHCSR enables the system handlers, and indicates:
• the pending status of the bus fault, memory management fault, and SVC exceptions
• the active status of the system handlers.
See the register summary in Table 654
for the SHCSR attributes. The bit assignments are
shown in Table 667
.
Table 663. System fault handler priority fields
Handler Field Register description
Memory management fault PRI_4 Table 664
Bus fault PRI_5
Usage fault PRI_6
SVCall PRI_11 Table 665
PendSV PRI_14 Table 666
SysTick PRI_15
Table 664. SHPR1 register bit assignments
Bits Name Function
[31:24] PRI_7 Reserved
[23:16] PRI_6 Priority of system handler 6, usage fault
[15:8] PRI_5 Priority of system handler 5, bus fault
[7:0] PRI_4 Priority of system handler 4, memory management fault
Table 665. SHPR2 register bit assignments
Bits Name Function
[31:24] PRI_11 Priority of system handler 11, SVCall
[23:0] - Reserved
Table 666. SHPR3 register bit assignments
Bits Name Function
[31:24] PRI_15 Priority of system handler 15, SysTick exception
[23:16] PRI_14 Priority of system handler 14, PendSV
[15:0] - Reserved