UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 592 of 841
NXP Semiconductors
UM10360
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
31.4.1.7 Channel hardware
Each stream is supported by a dedicated hardware channel, including source and
destination controllers, as well as a FIFO. This enables better latency than a DMA
controller with only a single hardware channel shared between several DMA streams and
simplifies the control logic.
31.4.1.8 DMA request priority
DMA channel priority is fixed. DMA channel 0 has the highest priority and DMA channel 7
has the lowest priority.
If the DMA Controller is transferring data for the lower priority channel and then the higher
priority channel goes active, it completes the number of transfers delegated to the master
interface by the lower priority channel before switching over to transfer data for the higher
priority channel. Transfers delegated to the master interface are staged in the DMA
channel FIFO, so the amount of data that needs to transfer could be as large as a 4
words.
It is recommended that memory-to-memory transactions use the lowest priority channel.
31.4.1.9 Interrupt generation
A combined interrupt output is generated as an OR function of the individual interrupt
requests of the DMA Controller and is connected to the interrupt controller.
31.4.2 DMA system connections
31.4.2.1 DMA request signals
The DMA request signals are used by peripherals to request a data transfer. The DMA
request signals indicate whether a single or burst transfer of data is required. The DMA
available request signals are:
DMACBREQ[15:0] — Burst request signals. These cause a programmed burst number
of data to be transferred.
DMACSREQ[15:0] — Single transfer request signals. These cause a single data to be
transferred. The DMA controller transfers a single transfer to or from the peripheral.
DMACLBREQ[15:0] — Last burst request signals.
DMACLSREQ[15:0] — Last single transfer request signals.
Note that peripherals on this device do not support “last” request types, and many do not
support both single and burst request types. See Section 31.4.2.3
.
31.4.2.2 DMA response signals
The DMA response signals indicate whether the transfer initiated by the DMA request
signal has completed. The response signals can also be used to indicate whether a
complete packet has been transferred. The DMA response signals from the DMA
controller are:
DMACCLR[15:0] — DMA clear or acknowledge signals. The DMACCLR signal is used by
the DMA controller to acknowledge a DMA request from the peripheral.
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