UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 535 of 841
NXP Semiconductors
UM10360
Chapter 25: LPC176x/5x Motor control PWM
25.7.7 MCPWM Match 0-2 registers (MCMAT0-2 - 0x400B 8030, 0x400B 8034,
0x400B 8038)
These registers also have “write” and “operating” versions as described above for the
Limit registers, and the operating registers are also compared to the channels’ TCs. See
25.7.6
above for details of reading and writing both Limit and Match registers.
The Match and Limit registers control the MCO0-2 outputs. If a Match register is to have
any effect on its channel’s operation, it must contain a smaller value than the
corresponding Limit register.
25.7.7.1 Match register in Edge-Aligned mode
If the channel’s CENTER bit in MCCON is 0 selecting edge-aligned mode, a match
between TC and MAT switches the channel’s B output from “active” to “passive” state. If
the channel’s CENTER and DTE bits in MCCON are both 0, the match simultaneously
switches the channel’s A output from “passive” to “active” state.
If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’s
deadtime counter to begin counting -- when the deadtime counter expires, the channel’s A
output switches from “passive” to “active” state.
25.7.7.2 Match register in Center-Aligned mode
If the channel’s CENTER bit in MCCON is 1 selecting center-aligned mode, a match
between TC and MAT while the TC is incrementing switches the channel’s B output from
“active” to “passive” state, and a match while the TC is decrementing switches the A
output from “active” to “passive”. If the channel’s CENTER bit in MCCON is 1 but the DTE
bit is 0, a match simultaneously switches the channel’s other output in the opposite
direction.
If the channel’s CENTER and DTE bits are both 1, a match between TC and MAT triggers
the channel’s deadtime counter to begin counting -- when the deadtime counter expires,
the channel’s B output switches from “passive” to “active” if the TC was counting up at the
time of the match, and the channel’s A output switches from “passive” to “active” if the TC
was counting down at the time of the match.
25.7.7.3 0 and 100% duty cycle
To lock a channel’s MCO outputs at the state “B active, A passive”, write its Match register
with a higher value than you write to its Limit register. The match never occurs.
To lock a channel’s MCO outputs at the opposite state, “A active, B passive”, simply write
0 to its Match register.
Table 474. MCPWM Match 0-2 registers (MCMAT0-2 - addresses 0x400B 8030, 0x400B 8034, 0x400B 8038) bit
description
Bit Symbol Description Reset value
31:0 MCMAT0/1/2 Match values for TC0, 1, 2. 0xFFFF FFFF
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