UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 148 of 841
NXP Semiconductors
UM10360
Chapter 10: LPC176x/5x Ethernet
Support for IEEE 802.3/clause 31 flow control is implemented in the flow control block.
Receive flow control frames are automatically handled by the MAC. Transmit flow control
frames can be initiated by software. In half duplex mode, the flow control module will
generate back pressure by sending out continuous preamble only, interrupted by pauses
to prevent the jabber limit from being exceeded.
The Ethernet block has a standard Reduced Media Independent Interface (RMII) to
connect to an external Ethernet PHY chip. Registers in the PHY chip are accessed via the
AHB interface through the serial management connection of the MIIM bus, typically
operating at 2.5 MHz.
10.8.2 Example PHY Devices
Some examples of compatible PHY devices are shown in Table 125.
10.9 Pin description
Table 126 shows the signals used for connecting the Reduced Media Independent
Interface (RMII) to the external PHY.
Table 127 shows the signals used for Media Independent Interface Management (MIIM) of
the external PHY.
Table 125. Example PHY Devices
Manufacturer Part Number(s)
Broadcom BCM5221
ICS ICS1893
Intel LXT971A
LSI Logic L80223, L80225, L80227
Micrel KS8721
National DP83847, DP83846, DP83843
SMSC LAN83C185
Table 126. Ethernet RMII pin descriptions
Pin Name Type Pin Description
ENET_TX_EN Output Transmit data enable
ENET_TXD[1:0] Output Transmit data, 2 bits
ENET_RXD[1:0] Input Receive data, 2 bits.
ENET_RX_ER Input Receive error.
ENET_CRS Input Carrier sense/data valid.
ENET_REF_CLK/
ENET_RX_CLK
Input Reference clock
Table 127. Ethernet MIIM pin descriptions
Pin Name Type Pin Description
ENET_MDC Output MIIM clock.
ENET_MDIO Input/Output MI data input and output
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