NXP Semiconductors LPC1768 - QEI Interrupt Enable Set Register (QEIIES - 0 X400 B CFDC)

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User manual Rev. 3 — 19 December 2013 557 of 841
NXP Semiconductors
UM10360
Chapter 26: LPC176x/5x Quadrature Encoder Interface (QEI)
26.6.4.5 QEI Interrupt Enable Set register (QEIIES - 0x400B CFDC)
Writing a 1 to a bit in this register sets the corresponding bit in the QEI Interrupt Enable
register (QEIIE).
4 ERR_Int Indicates that an encoder phase error was detected. 0
5 ENCLK_Int Indicates that and encoder clock pulse was detected. 0
6 POS0_Int Indicates that the position 0 compare value is equal to the current position. 0
7 POS1_Int Indicates that the position 1compare value is equal to the current position. 0
8 POS2_Int Indicates that the position 2 compare value is equal to the current position. 0
9 REV_Int Indicates that the index compare value is equal to the current index count. 0
10 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set
and the REV_Int is set.
0
11 POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set
and the REV_Int is set.
0
12 POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set
and the REV_Int is set.
0
31:13 - reserved 0
Table 503: QEI Interrupt Enable register (QEIIE - address 0x400B CFE4) bit description …continued
Bit Symbol Description Reset
value
Table 504: QEI Interrupt Enable Set register (QEIIES - address 0x400B CFDC) bit description
Bit Symbol Description Reset
value
0 INX_EN Indicates that an index pulse was detected. 0
1 TIM_EN Indicates that a velocity timer overflow occurred 0
2 VELC_EN Indicates that captured velocity is less than compare velocity. 0
3 DIR_EN Indicates that a change of direction was detected. 0
4 ERR_EN Indicates that an encoder phase error was detected. 0
5 ENCLK_EN Indicates that and encoder clock pulse was detected. 0
6 POS0_Int Indicates that the position 0 compare value is equal to the current position. 0
7 POS1_Int Indicates that the position 1compare value is equal to the current position. 0
8 POS2_Int Indicates that the position 2 compare value is equal to the current position. 0
9 REV_Int Indicates that the index compare value is equal to the current index count. 0
10 POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set
and the REV_Int is set.
0
11 POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set
and the REV_Int is set.
0
12 POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set
and the REV_Int is set.
0
31:13 - reserved 0