NXP Semiconductors LPC55S0x

This document, AN13033, provides hardware design guidelines for LPC55(S)xx microcontrollers, aiming to assist hardware engineers in designing and testing their processor-based systems. It offers board layout recommendations and design checklists to ensure successful first-pass designs and prevent board bring-up issues. The guide references relevant device-specific hardware documentation such as datasheets, reference manuals, and other application notes available on nxp.com.

The LPC55Sxx/LPC55xx family of microcontrollers is built around the Arm® Cortex®-M33 core, incorporating PowerQuad Accelerator and CASPER Accelerator. The 'S' in the part name indicates support for enhanced security features, including TrustZone. The family offers various core frequencies, with LPC55S0x/LPC550x operating at 96 MHz and LPC55S1x/LPC551x, LPC55S2x/LPC552x, and LPC55S6x/LPC556x operating at 150 MHz. The higher-frequency parts (LPC55S2x/LPC552x and LPC55S6x/LPC556x) also feature dual cores, PowerQuad, and CASPER accelerators.

In terms of peripherals, all LPC55Sxx/LPC55xx devices include 8 Flexcomm interfaces and 1 50 MHz HS-SPI. The LPC55S1x/LPC551x, LPC55S2x/LPC552x, and LPC55S6x/LPC556x models additionally offer 1 HS USB, 1 FS USB, and 1 CAN FD interface. For timers, all family members provide 5 CTimers, 1 SCT, 1 MRT, 1 WWDT, 1 Code WDT, 1 RTC, and 1 OS-Timer. Analog peripherals across the family include a 16-bit ADC (10 channels) and a 1 comparator (5 inputs). The LPC55S0x/LPC550x and LPC55S1x/LPC551x ADCs operate at 2 Msps, while the LPC55S2x/LPC552x and LPC55S6x/LPC556x ADCs operate at 1 Msps. A 12-bit DAC is also available on all models except the LPC55S0x/LPC550x. The devices are available in various packages, including HVQFN 48, HVQFN 64, HTQFP 64, VFBGA 98, HLQFP 100, HLQFP 144, and VBGA 196, with specific package availability varying by family member.

The power supply for the LPC55Sxx series requires a single 1.8 V to 3.6 V operating voltage. For LPC55S0x/LPC550x, LPC55S1x/LPC551x, LPC55S2x/LPC552x, and LPC55S6x/LPC556x, the internal core voltage is supplied by an internal DC/DC regulator, which necessitates an external inductance and two or three capacitors. The document provides a schematic for using the internal DC/DC converter, showing connections for VBAT_PMU, VBAT_DCDC, VDD_PMU, FB, LX, VSS_PMU, and VSS_DCDC, along with recommended capacitor and inductor values (e.g., C1, C2: 22 µF; C3: 100 nF; C4: 47 pF; L1: 4.7 µH).

Detailed power domain information and decoupling capacitor recommendations are provided. For USB0 Analog 3.3 V and USB1 Analog 3.3 V supplies, a 3.3 V voltage is used with a 10 µF bulk/bypass capacitor and a 0.1 µF decoupling capacitor per pin (X7R Ceramic). For the single power supply powering I/Os (VDD), a 1.8-3.3 V voltage is used with a 10 µF bulk/bypass capacitor and a 0.1 µF decoupling capacitor per pin (X7R Ceramic). The core supply (VBAT_PMU) for applications with the DCDC converter requires 22 µF + 100 nF + 47 pF (X7R Ceramic). Analog supply voltage (VDDA) uses 1.8-3.6 V with 10 µF bulk/bypass and 0.1 µF decoupling capacitors. ADC positive reference (VREFP) uses 0.985-VDDA with 10 µF bulk/bypass and 0.1 µF decoupling capacitors. VSS, VSSA, and VREFN must be shorted to GND at the package level. The effectiveness of bulk/bypass and decoupling capacitors relies on optimal placement and connection, with all decoupling capacitors placed as close as possible to their respective power supply pins, and their ground sides connected directly to the internal ground plane via a via.

The clock circuitry section describes the various clock sources available, including the Internal Free Running Oscillator (FRO) providing selectable 96 MHz and 12 MHz outputs (trimmed to +/- 2% accuracy), a 32 kHz Internal FRO (trimmed to +/- 2% accuracy), and a 1 MHz Internal Low Power Oscillator (trimmed to +/- 15% accuracy). Crystal oscillators are supported for 16 MHz or 32 MHz operation, with an option for external clock input (bypass mode) up to 24 MHz. A 32.768 kHz crystal oscillator is also available, with an external clock input option up to 100 kHz. PLL0 and PLL1 allow CPU operation up to the maximum CPU rate, sourcing from the internal FRO 12 MHz output, external oscillator, internal FRO 1 MHz output, or the 32.768 kHz RTC oscillator. The document notes that for external crystal and RTC oscillators, LPC55Sxx devices have a capacitor bank feature, allowing stabilizing capacitors to be unsoldered on both 32 K and 16 MHz XTAL. It is suggested to keep these capacitors as DNP/Do Not Populate on the PCB.

For crystal oscillator design, the crystal (XTAL) and capacitances CX1 and CX2 are connected externally to XTAL32M_P and XTAL32M_N. In bypass mode, an external clock can be connected to XTAL32M_P if XTAL32M_N is left open. The values for CX1 and CX2 can be determined by the formula: CX1 = CX2 = 2CL (CPad + CParasitic), where CL is the crystal load capacitance, CPad is the pad capacitance (~3 pF), and CParasitic is the parasitic capacitance of the external circuit. PCB design guidelines for oscillators emphasize placing components as close as possible to the chip's input/output pins, keeping trace lengths short, ensuring a common ground plane for load capacitors, minimizing loops for noise reduction, and laying out a ground pattern under the crystal unit without other signal lines. Similar guidelines apply to the RTC oscillator circuit, which uses a 32.768 kHz crystal and external capacitances CX1 and CX2 connected to XTAL32K_P and XTAL32K_N.

Boot mode configurations are detailed, with the internal ROM memory storing the boot code executed after reset or power-on. The bootloader decides whether to boot from internal flash or enter ISP mode based on CMPA bits, ISP pin (PIO0_5), and image header type. If PIO0_5 is HIGH, the device attempts a passive boot from internal flash; if no valid image is found, it enters ISP boot mode. If PIO0_5 is LOW, it enters ISP boot mode, allowing image download via serial interfaces (UART0, I2C1, SPI3, HS_SPI, USB0, USB1). Specific pin assignments for USART, I2C, and SPI ISP modes are provided, which are fixed by the ROM code.

The debug and programming interface section describes common debug connectors. For LPC55Sxx, a 0.05" 10-pin Samtec FTSH-105 connector is recommended for debug, supporting both JTAG and Serial-Wire Debug (SWD) protocols. The JTAG functions (TRST, TCK, TMS, TDI, TDO) are selected on PIO0_2 to PIO0_6 in boundary scan mode but cannot be used for debug mode. SWD/SWV pins are overlaid on JTAG pins. SWD signals include SWCLK (PIO0_11, input, pull-down), SWDIO (PIO0_12, input, pull-up), SWO (PIO0_8, output, Z), and RESET (dedicated pin, pull-up). External pull-up/down resistors for JTAG signals can be added to increase debugger connection robustness.

Communication modules include the CAN-FD interface for LPC55S1x devices, which fully implements the CAN protocol specification, CAN with Flexible Data rate (CAN FD), and CAN 2.0 version B protocol. It supports standard and extended message frames and long payloads up to 64 bytes, with transfer rates up to 8 Mbps. The physical layer characteristics are specified in ISO-11898-2, recommending parallel wires with a nominal impedance of 120 Ω. Shielded twisted pair cables are generally necessary for EMC reasons.

For analog features, the ADC impedance is discussed, with a block diagram showing the simplified input pin equivalent circuit and channel select circuit. The datasheet provides RADIN values for fast input channels (PIO0_16/PIO0_23, PIO0_11/PIO0_10, PIO0_12/PIO0_15, PIO1_0/PIO0_31) ranging from 1 kΩ to 2 kΩ (typical to max), and for standard input channels (PIO1_9/PIO1_8) ranging from 1.4 kΩ to 3.6 kΩ.

General recommendations cover pin termination and PCB layout. All pins have pull-ups, pull-downs, and inputs turned off at reset, except for PIO0_2, PIO0_5, PIO0_11, PIO0_12, PIO0_13, and PIO0_14. Unused pins should be terminated to minimize power consumption; GPIO pins should be configured as outputs set to LOW with internal pull-up disabled. XTAL32K_P should be connected to ground to disable the RTC oscillator, and XTAL32K_N can be left unconnected. VREFN should be tied to VSS, VDDA to VBAT_DCDC, and VSSA to VSS. USBn_DP and USBn_DM can be left unconnected, while USBn_3V3, USB1_VBUS, and USBn_VSS should be tied to VBAT_DCDC and VSS, respectively.

PCB layout guidelines recommend using a multilayer PCB with dedicated ground (VSS) and VDD supply layers for good decoupling and shielding. Traces should avoid right-angle bends, preferring two 45° corners or round bends to minimize impedance changes and reflections. Grounding techniques emphasize a solid and unbroken ground plane, avoiding splits for analog, digital, and power pins. Floating metal/shapes near microcontroller pins should be eliminated by filling unused copper areas with ground and connecting them to the ground plane through vias. EMI/EMC and ESD considerations are crucial, with recommendations including adequate filter capacitors with low equivalent series inductance (ESL), creating ground planes, keeping current loops small, and isolating high-speed signals from input/output ports. For optimal signal integrity, a four-layer PCB is recommended for Ethernet applications, with specific layer stack-ups provided for four, six, and eight-layer boards. Finally, the document reminds users that internal ESD diodes are for short discharge pulses only, and input signals must remain within specified electrical parameters to prevent unexpected behavior or damage to the MCU.