NXP Semiconductors LPC55S0x User Manual

1 Introduction
This document guides the hardware engineers to design and test their
LPC55(S)xx processor-based designs. The document provides information
about board layout recommendations and design checklists to ensure first
pass success and avoid any board bring-up problems.
This guide is released with the relevant device-specific hardware
documentation such as data sheets, reference manuals, and application notes
available on nxp.com.
2 LPC55(S)xx family comparison
All LPC55Sxx/LPC55xx family is based on Arm
®
Cortex
®
-M33 core, with
PowerQuad Accelerator and CASPER Accelerator. The S in the middle
of part name means this part provides more security features, such as
TrustZone Support.
Table 1. LPC55Sxx family core features
Family Core
frequency
Dual
core
Power
Quad
CASPER
LPC55S0x/LPC550x 96 MHz — — YES
LPC55S1x/LPC551x 150 MHz
— —
YES
LPC55S2x/LPC552x 150 MHz YES YES YES
LPC55S6x/LPC556x 150 MHz YES YES YES
Table 2. LPC55Sxx/LPC55xx peripherals
Family Flexcomm 50 MHz HS-
SPI
HS USB FS USB CAN FD SDIO
LPC55S0x/LPC550x 8 1
— —
1
—
LPC55S1x/LPC551x 8 1 1 1 1
—
LPC55S2x/LPC552x 8 1 1 1
—
1
LPC55S6x/LPC556x 8 1 1 1
—
1
Contents
1 Introduction......................................1
2 LPC55(S)xx family comparison.......1
3 Power supply...................................2
3.1 Introduction.................................. 2
3.2 Bulk and decoupling capacitors... 5
4 Clock circuitry..................................6
4.1 Introduction.................................. 6
4.2 Crystal oscillator...........................7
4.3 RTC oscillator.............................. 8
4.4 Common suggestions for the PCB
layout of oscillator circuit............10
5 Boot mode configurations............. 10
5.1 Boot mode selection.................. 11
6 Debug and programing interface...12
6.1 Debug connector pinouts...........14
7 Communication modules...............14
7.1 CAN interface for CAN-FD module
...................................................14
8 Analog........................................... 15
8.1 ADC impedance.........................15
9 Recommendations........................ 16
9.1 Pin descriptions..........................16
9.2 Termination of unused pins....... 17
9.3 PCB............................................18
9.4 General board layout guidelines
...................................................18
10 References....................................23
11 Revision history.............................23
AN13033
Hardware Design Guidelines for LPC55(S)xx Microcontrollers
Rev. 0 — 30 October 2020
Application Note

NXP Semiconductors LPC55S0x Specifications

General

Brand	NXP Semiconductors
Model	LPC55S0x
Category	Microcontrollers
Language	English

Summary

Introduction

LPC55(S)xx Family Comparison

Power Supply

3.1 Introduction

Overview of the LPC55Sxx series power supply requirements and internal regulator.

3.2 Bulk and Decoupling Capacitors

Guidance on selecting and placing bulk and decoupling capacitors for stable power supply.

Clock Circuitry

4.1 Introduction

Overview of the clock sources available for the LPC55S1x/2x/6x microcontrollers.

4.2 Crystal Oscillator and PCB Design

Details on crystal oscillator, its PCB layout, and component selection.

4.3 RTC Oscillator and PCB Design

Details on RTC oscillator connection and its PCB layout recommendations.

4.4 Common Suggestions for Oscillator PCB Layout

General advice for designing the PCB layout of oscillator circuits.

Boot Mode Configurations

5.1 Boot Mode Selection

Explains how to select boot mode based on ISP pin states and internal ROM memory.

Debug and Programming Interface

6.1 Debug Connector Pinouts

Details on commonly used debug connectors and their pinouts for JTAG/SWD.

Communication Modules

7.1 CAN Interface for CAN-FD Module

Physical layer characteristics and system overview for CAN-FD interface.

Analog

8.1 ADC Impedance

Details on the ADC block diagram and input resistance values.

Recommendations

9.1 Pin Descriptions and Configurations

Details pin functions, pull-up/down states, open-drain, wakeup, and JTAG configurations.

9.2 Termination of Unused Pins

Recommendations for terminating unused pins to minimize power consumption.

9.3 PCB

Technical reasons for using multilayer PCBs with dedicated ground and VDD layers.

9.4 Board Layout and Design Guidelines

Covers traces, grounding, EMI/EMC, layer stacking, and injection current.

References

Revision History