NXP Semiconductors MPC5777M - User Manual

NXP Semiconductors
Data Sheet: Technical Data
Document Number: MPC5777M
Rev. 6, 06/2016
NXP reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
MPC5777M
416 TEPBGA
27mm x 27 mm
512 TEPBGA
25 mm x 25 mm
• Three main CPUs, single issue, 32-bit CPU core complexes
(e200z7), one of which is a dedicated lockstep core.
– Power Architecture
®
embedded specification
compliance
– Instruction set enhancement allowing variable length
encoding (VLE), encoding a mix of 16-bit and 32-bit
instructions, for code size footprint reduction
– Single-precision floating point operations
– 16 KB Local instruction RAM and 64 KB local data
RAM
– 16 KB I-Cache and 4 KB D-Cache
• I/O Processor, dual issue, 32-bit CPU core complex
(e200z4), with
– Power Architecture embedded specification compliance
– Instruction set enhancement allowing variable length
encoding (VLE), encoding a mix of 16-bit and 32-bit
instructions, for code size footprint reduction
– Single-precision floating point operations
– Lightweight Signal Processing Auxiliary Processing
Unit (LSP APU) instruction support for digital signal
processing (DSP)
– 16 KB Local instruction RAM and 64 KB local data
RAM
– 8 KB I-Cache
• 8640 KB on-chip flash
– Supports read during program and erase operations, and
multiple blocks allowing EEPROM emulation
• 404 KB on-chip general-purpose SRAM including 64 KB
standby RAM (+ 192 KB data RAM included in the
CPUs). Of this 404 KB, 64 KB can be powered by a
separate supply so the contents of this portion can be
preserved when the main MCU is powered down.
• Multichannel direct memory access controllers (eDMA): 2
x 64 channels per eDMA (128 channels total)
• Triple Interrupt controller (INTC)
– Dual phase-locked loops with stable clock domain for
peripherals and FM modulation domain for
computational shell
• Dual crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus masters with
end-to-end ECC
• Hardware Security Module (HSM) to provide robust
integrity checking of flash memory
• System Integration Unit Lite (SIUL)
• Boot Assist Module (BAM) supports factory programming
using serial bootload through ‘UART Serial Boot Mode
Protocol’. Physical interface (PHY) can be:
– UART/LIN
–CAN
• GTM104 — generic timer module
• Enhanced analog-to-digital converter system with
– Twelve separate 12-bit SAR analog converters
– Ten separate 16-bit Sigma-Delta analog converters
• Eight deserial serial peripheral interface (DSPI) modules
• Two Peripheral Sensor Interface (PSI5) controllers
• Three LIN and three UART communication interface
(LINFlexD) modules (6 total)
– LINFlexD_0 is a Master/Slave
– LINFlexD_1, LINFlexD_2, LINFlexD_14,
LINFlexD_15, and LINFlexD_16 are Masters
• Four modular controller area network (MCAN) modules
and one time-triggered controller area network
(M-TTCAN)
• External Bus Interface (EBI)
– Dual routing of accesses to EBI
– Access path determined by access address
– Access path downstream of PFLASH controller
– Allows EBI accesses to share buffer and prefetch
capabilities of internal flash
– Allows internal flash accesses to be remapped to
memories connected to EBI
MPC5777M Microcontroller
Data Sheet

Summary

Package pinouts and signal descriptions

Package pinouts

Illustrates BGA ballmap package pinouts for production and emulation devices.

Pin;ball descriptions

Power supply and reference voltage pins;balls

Lists power supply and reference pin functions for the MPC5777M devices.

System pins;balls

Electrical characteristics

Absolute maximum ratings

Describes the absolute maximum ratings of the MPC5777M device.

Operating conditions

DC electrical specifications

Details the DC electrical specifications for the MPC5777M microcontroller.

I;O pad specification

Describes the different I/O pad configurations for the MPC5777M.

I;O input DC characteristics

I;O output DC characteristics

ADC specifications

Provides specifications for the Analog-to-Digital Converters (ADC).

SAR ADC electrical specification

S;D ADC electrical specification

LVDS Fast Asynchronous Serial Transmission (LFAST) pad electrical characteristics

LFAST and MSC;DSPI LVDS interface electrical characteristics

Power management: PMC, POR;LVD, sequencing

Covers power management features including PMC, POR/LVD, and sequencing.

Power management electrical characteristics

Device voltage monitoring

Power up;down sequencing

Flash memory electrical characteristics

Covers electrical specifications for the flash memory.

Flash memory program and erase specifications

Details estimated program/erase times and specifications.

Flash memory FERS program and erase specifications

Provides FERS program and erase specifications.

Flash memory Array Integrity and Margin Read specifications

Flash memory AC timing specifications

Details AC timing specifications for flash memory operations.

AC specifications

Covers all AC timing specifications for the MPC5777M.

Debug and calibration interface timing

DSPI timing with CMOS and LVDS pads

Shows DSPI channel frequency support and timing with CMOS/LVDS pads.

FEC timing

Covers timing specifications for the Fast Ethernet Controller (FEC).

FlexRay timing

Details FlexRay interface timing characteristics for input and output signals.

External Bus Interface (EBI) Timing

I2 C timing

Thermal characteristics

Ordering information

NXP Semiconductors MPC5777M Specifications

General

Brand	NXP Semiconductors
Model	MPC5777M
Category	Microcontrollers
Language	English