NXP Semiconductors MPC5777M - LFAST Interface Timing Diagrams

Electrical characteristics
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 67
3.12.1 LFAST interface timing diagrams
Figure 16. LFAST and MSC/DSPI LVDS timing definition
Signal excursions above this level NOT allowed
Max. common mode input at RX
Signal excursions below this level NOT allowed
Min. common mode input at RX
Data Bit Period
Minimum Data Bit Time
Opening =
0.55 * T (LFAST)
0.50 * T (MSC/DSPI)
Max Differential Voltage =
285 mV p-p (LFAST)
400 mV p-p (MSC/DSPI)
Min Differential Voltage =
100 mV p-p (LFAST)
150 mV p-p (MSC/DSPI)
1743 mV
1600 mV
V
OS
= 1.2 V +/- 10%
TX common mode
V
ICOM
150 mV
0V
1743 mV
“No-Go” Area
T = 1 /F
DATA

VOD


VOD

PER
EYE
PER
EYE