NXP Semiconductors MPC5777M - AC specifications; Debug and calibration interface timing

Electrical characteristics
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 85
3.16 AC specifications
All AC timing specifications are valid up to 150 °C, except where explicitly noted.
3.16.1 Debug and calibration interface timing
3.16.1.1 JTAG interface timing
Table 45. Flash Read Wait State and Address Pipeline Control Combinations
Flash Frequency RWSC setting APC setting
0 MHz < fFLASH  33 MHz 0 0
33 MHz < fFLASH  100 MHz 2 1
100 MHz < fFLASH  133 MHz 3 1
133 MHz < fFLASH  167 MHz 4 1
167 MHz < fFLASH  200 MHz 5 2
Table 46. JTAG pin AC electrical characteristics
1,2
1
These specifications apply to JTAG boundary scan only. See Table 47 for functional specifications.
2
JTAG timing specified at V
DD_HV_IO_JTAG
= 4.0 V to 5.5 V, and maximum loading per pad type as specified in the
I/O section of the data sheet.
# Symbol Characteristic
Value
Unit
Min Max
1t
JCYC
CC TCK cycle time 100 — ns
2t
JDC
CC TCK clock pulse width 40 60 %
3t
TCKRISE
CC TCK rise and fall times (40%–70%) — 3 ns
4t
TMSS,
t
TDIS
CC TMS, TDI data setup time 5 — ns
5t
TMSH,
t
TDIH
CC TMS, TDI data hold time 5 — ns
6t
TDOV
CC TCK low to TDO data valid — 16
3
3
Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
ns
7t
TDOI
CC TCK low to TDO data invalid 0 — ns
8t
TDOHZ
CC TCK low to TDO high impedance — 15 ns
9t
JCMPPW
CC JCOMP assertion time 100 — ns
10 t
JCMPS
CC JCOMP setup time to TCK low 40 — ns
11 t
BSDV
CC TCK falling edge to output valid — 600
4
ns
12 t
BSDVZ
CC TCK falling edge to output valid out of high impedance — 600 ns
13 t
BSDHZ
CC TCK falling edge to output high impedance — 600 ns
14 t
BSDST
CC Boundary scan input valid to TCK rising edge 15 — ns
15 t
BSDHT
CC TCK rising edge to boundary scan input invalid 15 — ns