NXP Semiconductors MPC5777M - 5 Document Revision History

MPC5777M Microcontroller Data Sheet, Rev. 6
Document revision history
NXP Semiconductors136
5 Document revision history
Table 76 summarizes revisions to this document.
Table 76. Revision history
Revision Date Description of changes
1 12/2011 Initial release
2 4/2013
Throughout
• Data sheet now includes both KGD (T
J
165 °C) and non-KGD (T
J
150 °C)
specifications
• The interfaces and components formerly including the name “DigRF” have been
renamed to “LFAST.”
Introduction
• Changed on-chip general-purpose SRAM to 404 KB (was 384 KB)
• Changed item describing Boot Assist Flash support to “Boot Assist Module (BAM)
supports factory programming using serial bootload through ’UART Serial Boot Mode
Protocol’. Physical interface (PHY) can be: UART/LIN, CAN, FlexRay”
Table 1 (Family comparison):
• Changed feature from “Zipwire/LFAST
7
bus” to “Zipwire (SIPI / LFAST
7
) Interprocessor
Communication Interface”
Figure 1 (Block diagram):
• Changed SRAM from 320 to 340 KB
• Changed figure to include “Triple INTC”
• Added “LFAST Switch” block to Computational Shell
• Added “Debug SIPI” block to the Peripheral Domain 50 MHz Concentrator
Figure 2 (Periphery allocation):
• Added PSI5_S_0 module
• Changed “Peripheral Cluster A” to “Peripheral Cluster B” and “Peripheral Cluster B” to
“Peripheral Cluster A”
• Added PSI5_S_0 module
Package pinouts and signal descriptions
Figure 3 (292-ball BGA production device pinout (top view))
Figure 4 (292-ball BGA emulation device pinout (top view))
Figure 5 (512-ball BGA production device pinout (top view))
Figure 8 (512-ball BGA emulation device pinout (top view)):
• Changed “VDD_HV_PMC_BYP” to “VDD_HV_IO_MAIN”
Table 2 (Power supply and reference pins):
• Removed V
DD_HV_PMC_BYP
(PMC Voltage Supply Bypass Capacitor) row.
Table 3 (System pins):
• Clarification of TESTMODE pin definition: “TESTMODE pull-down is implemented to
prevent the device from entering TESTMODE. It is recommended to connect the
TESTMODE pin to VSS_HV_IO on the board. The value of the TESTMODE pin is
latched at the negation of reset and has no affect afterward. The device will not exit
reset with the TESTMODE pin asserted during power-up.” (Added detail regarding
when TESTMODE pin value is latched and that device will not exit reset when pin is
asserted during power-up)