NXP Semiconductors MPC5777M - DSPI timing with CMOS and LVDS pads

Electrical characteristics
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 93
3.16.2 DSPI timing with CMOS and LVDS
1
pads
DSPI channel frequency support is shown in Table 50. Timing specifications are shown in Table 51, Table 52, Table 54,
Table 55 and Table 56.
3.16.2.1 DSPI master mode full duplex timing with CMOS and LVDS pads
3.16.2.1.1 DSPI CMOS Master Mode – Classic Timing
1. DSPI in TSB mode with LVDS pads can be used to implement Micro Second Channel bus protocol.
Table 50. DSPI channel frequency support
DSPI use mode
Max usable
frequency (MHz)
1,2
1
Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.
2
Maximum usable frequency does not take into account external device propagation delay.
CMOS (Master mode) Full duplex – Classic timing (Table 51)17
Full duplex – Modified timing (Table 52)30
Output only mode (SCK/SOUT/PCS) (Table 51 and Table 52)30
Output only mode TSB mode (SCK/SOUT/PCS) (Table 56)30
LVDS (Master mode)
3
3
µS Channel and LVDS timing is not supported for DSPI12.
Full duplex – Modified timing (Table 54)33
Output only mode TSB mode (SCK/SOUT/PCS) (Table 55)40
Table 51. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 1
1
# Symbol Characteristic
Condition Value
2
Unit
Pad drive
3
Load (C
L
)Min Max
1t
SCK
CC SCK cycle time SCK drive strength
Very strong 25 pF 33.0 — ns
Strong 50 pF 80.0 —
Medium 50 pF 200.0 —
2t
CSC
CC PCS to SCK delay SCK and PCS drive strength
Very strong 25 pF (N
4
× t
SYS
5
)–16 —ns
Strong 50 pF (N
4
× t
SYS
5
)–16 —
Medium 50 pF (N
4
× t
SYS
5
)–16 —
PCS medium
and SCK strong
PCS = 50 pF
SCK = 50 pF
(N
4
× t
SYS
5
)–29 —