NXP Semiconductors MPC5777M - Page 94

MPC5777M Microcontroller Data Sheet, Rev. 6
Electrical characteristics
NXP Semiconductors94
3t
ASC
CC After SCK delay SCK and PCS drive strength
Very strong PCS = 0 pF
SCK = 50 pF
(M
6
× t
SYS
5
)–35 —ns
Strong PCS = 0 pF
SCK = 50 pF
(M
6
× t
SYS
5
)–35 —
Medium PCS = 0 pF
SCK = 50 pF
(M
6
× t
SYS
5
)–35 —
PCS medium
and SCK strong
PCS = 0 pF
SCK = 50 pF
(M
6
× t
SYS
5
)–35 —
4t
SDC
CC SCK duty cycle
7
SCK drive strength
Very strong 0pF
1
/
2
t
SCK
–2
1
/
2
t
SCK
+2 ns
Strong 0pF
1
/
2
t
SCK
–2
1
/
2
t
SCK
+2
Medium 0pF
1
/
2
t
SCK
–5
1
/
2
t
SCK
+5
PCS strobe timing
5t
PCSC
CC PCSx to PCSS
time
8
PCS and PCSS drive strength
Strong 25 pF 16.0 —ns
6t
PASC
CC PCSS to PCSx
time
8
PCS and PCSS drive strength
Strong 25 pF 16.0 —ns
SIN setup time
7t
SUI
CC SIN setup time to
SCK
9
SCK drive strength
Very strong 25 pF 25.0 — ns
Strong 50 pF 32.75 —
Medium 50 pF 52.0 —
SIN hold time
8t
HI
CC SIN hold time from
SCK
9
SCK drive strength
Very strong 0pF –1.0 — ns
Strong 0pF –1.0 —
Medium 0pF –1.0 —
SOUT data valid time (after SCK edge)
9t
SUO
CC SOUT data valid
time from SCK
10
SOUT and SCK drive strength
Very strong 25 pF — 7.0 ns
Strong 50 pF — 8.0
Medium 50 pF — 16.0
SOUT data hold time (after SCK edge)
Table 51. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 1
1
# Symbol Characteristic
Condition Value
2
Unit
Pad drive
3
Load (C
L
)Min Max