NXP Semiconductors MPC5777M - System pins;balls

Package pinouts and signal descriptions
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 15
2.2.2 System pins/balls
Table 3 contains information on system pin functions for the devices.
V
DD_HV_IO_FLEX
Power FlexRay/Ethernet 3.3 V I/O
supply
D7 J10
V
DD_HV_IO_FLEXE
Power FLexRay/Ethernet/EBI I/O
Segment Voltage Supply
AC18, AC22 AJ11, AK11, AK20,
AK29
V
DD_HV_IO_EBI
Power EBI Address/Control I/O Segment
Voltage Supply
M23,T23,Y23 J29, J30, V30, AH30
V
DD_HV_FLA
Power Decoupling supply pin for flash A18, B18 J21, K20
V
SS_HV_ADV_S
Ground Ground supply for ADC SAR AF9 AE9, AJ8
V
DD_HV_ADV_S
Power Voltage supply for ADC SAR AE9 AE10, AJ9
V
SS_HV_ADV_D
Ground Ground supply for ADC SD AF5 AK8
V
DD_HV_ADV_D
Power Voltage supply for ADC SD AE5 AK9
V
SS_HV_ADR_S
Reference Ground reference for ADC SAR AE8 AE12
V
DD_HV_ADR_S
Reference Voltage reference for ADC SAR AF8 AE11
V
SS_HV_ADR_D
Reference Ground reference for ADC SD Y4, AC6 AA7
V
DD_HV_ADR_D
Reference Voltage reference for ADC SD W4, AD6 AA6
V
DDSTBY
Power Standby RAM supply AD9 AA16
Table 3. System pins
Symbol Description Direction
BGA ball
416PD 416ED 512PD 512ED
PORST Power on reset with Schmitt trigger
characteristics and noise filter. PORST is
active low
Bidirectional B22 M22
ESR0 External functional reset with Schmitt
trigger characteristics and noise filter.
ESR0 is active low
Bidirectional A23 L21
TESTMODE Pin for testing purpose only. TESTMODE
pull-down is implemented to prevent the
device from entering TESTMODE. It is
recommended to connect the
TESTMODE pin to VSS_HV_IO on the
board. The value of the TESTMODE pin
is latched at the negation of reset and has
no affect afterward.
Note: The device will not exit reset with
the TESTMODE pin asserted
during power-up.
Input only B23 N24
Table 2. Power supply and reference pins (continued)
Supply BGA ball
Symbol Type Description 416PD 416ED 512PD 512ED