NXP Semiconductors MPC5777M - PSI5 Timing; UART Timing

Electrical characteristics
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 117
3.16.4.3 RxD
3.16.5 PSI5 timing
The following table describes the PSI5 timing.
3.16.6 UART timing
UART channel frequency support is shown in the following table.
Table 66. RxD input characteristics
1
1
FlexRay RxD timing is valid for Automotive input levels with hysteresis enabled (hysteresis permanently enabled in
Automotive input levels) and CMOS input levels with hysteresis disabled, 4.5 V  V
DD_HV_IO
 5.5 V for both cases.
Symbol Characteristic
Value
Unit
Min Max
C_CCRxD CC Input capacitance on RxD pin
—7pF
uCCLogic_1 CC Threshold for detecting logic high
35 70 %
uCCLogic_0 CC Threshold for detecting logic low
30 65 %
dCCRxD
01
CC Sum of delay from actual input to the D input of the first
FF, rising edge
—10ns
dCCRxD
10
CC Sum of delay from actual input to the D input of the first
FF, falling edge
—10ns
dCCRxAsymAccept15 CC Acceptance of asymmetry at receiving CC with 15 pF
load
–31.5 44 ns
dCCRxAsymAccept25 CC Acceptance of asymmetry at receiving CC with 25 pF
load
–30.5 43 ns
Table 67. PSI5 timing
Symbol Parameter
Value
Unit
Min Max
t
MSG_DLY
CC Delay from last bit of frame (CRC0) to assertion
of new message received interrupt
—3 µs
t
SYNC_DLY
CC Delay from internal sync pulse to sync pulse
trigger at the SDOUT_PSI5_n pin
—2 µs
t
MSG_JIT
CC Delay jitter from last bit of frame (CRC0) to
assertion of new message received interrupt
— 1 cycles
1
1
Measured in PSI5 clock cycles (PBRIDGEn_CLK on the device). Minimum PSI5 clock period is 20 ns.
t
SYNC_JIT
CC Delay jitter from internal sync pulse to sync pulse
trigger at the SDOUT_PSI5_n pin
— ±(1 PSI5_1µs_CLK +
1 PBRIDGEn_CLK)
cycles