Electrical characteristics
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 29
3.6 I/O pad specification
The following table describes the different pad type configurations.
9
V
DDSTBY
may be supplied with a non-regulated power supply, but the absolute maximum voltage on VDDSTBY given in
the absolute maximum ratings table must be observed.
10
Standby current is reduced by a factor of two from T
J
=150 °C, for approximately every ~20 °C drop in operating
temperature.
11
The maximum value for I
DDSTBY_ON
is also valid when switching from the core supply to the standby supply, and when
powering up the device and switching the RAM supply back to V
DD_LV
.
12
The standby RAM regulator current is present on the VDDSTBY pin whenever a voltage is applied to the pin. This also
applies to normal operation where the RAM is powered by the VDD_LV supply. Connecting the VDDSTBY pin to ground
when not using the standby RAM feature will remove the leakage current on the VDDSTBY pin.
13
If Aurora and JTAGM/LFAST not used, V
DD_LV_BD
current is reduced by ~20mA.
14
Applies to 2MB calibration RAM in the BD.
15
Buddy device leakage dependency on temperature can be estimated by dividing the 150 °C leakage by two for each
temperature drop of ~20 °C.
16
Current spike may occur during normal operation that are above average current, valid for I
DDAPP
and its conditions given
in Table 10 (DC electrical specifications). Internal schemes must be used (eg frequency ramping, feature enable) to
ensure that incremental demands are made on the external power supply. An internal fast regulator providing ~40mA peak
current within 1us to filter any core power supply droops is available on the device. Assumption is minimum 13.3 µF (20 µF
typical) capacitance on the core supply.]
17
Moving window, valid for I
DDAPP
and its conditions given in Table 10 (DC electrical specifications), with a maximum of
90 mA for the worst case application
18
This specification is the maximum value and is a boundary for the dl specification.
19
Condition1: For power on period from 0 V up to normal operation with reset asserted. Condition 2: From reset asserted
until PLL running free. Condition 3: Increasing PLL from free frequency to full frequency. Condition 4: reverse order for
power down to 0 V.
20
I
DDOFF
is the minimum guaranteed consumption of the device during power-up. It can be used to correctly size power-off
ballast in case of current injection during power-off state.Power up/down current transients can be limited by controlling
the clock ramp rates with the Progressive Clock Frequency Switching block on the device.
21
V
STBY_BO
is the maximum voltage that sets the standby RAM brown-out flag in the device logic. The minimum voltage for
RAM data retention is guaranteed to always be less than the V
STBY_BO
maximum value.
22
The temperature coefficient and line regulation specifications are used to calculate the reference voltage drift at an
operating point within the specified voltage and temperature operating conditions.
Table 11. I/O pad specification descriptions
Pad type Description
Weak configuration Provides a good compromise between transition time and low electromagnetic emission.
Pad impedance is centered around 800
Medium configuration Provides transition fast enough for the serial communication channels with controlled
current to reduce electromagnetic emission.
Pad impedance is centered around 200
Strong configuration Provides fast transition speed; used for fast interface.
Pad impedance is centered around 50
Very strong configuration Provides maximum speed and controlled symmetric behavior for rise and fall transition.
Used for fast interface including Ethernet, FlexRay, and the EBI data bus interfaces
requiring fine control of rising/falling edge jitter.
Pad impedance is centered around 40
EBI configuration Provides necessary speed for fast external memory interfaces on the EBI address and
control signals. Drive strength is matched to four selectable loads.
To Next Page
Loading...
