NXP Semiconductors MPC5777M - Power up;down sequencing

MPC5777M Microcontroller Data Sheet, Rev. 6
Electrical characteristics
NXP Semiconductors78
3.14.5 Power up/down sequencing
Table 38 shows the constraints and relationships for the different power supplies
During power-up, all functional terminals are maintained into a known state as described within the following table.
6
This specification is driven by LVD108_C. There are additional LVDs on PLL and Flash VDD_LV supply nets which will
assert at voltage below LVD108_C.
7
LV external supply levels are measured on the die side of the package bond wire after package voltage drop. This is
monitoring external regulator supply voltage and board voltage drop. This does not guarantee device is working down
to minimum threshold. For minimum supply, refer to operating condition table.
8
HVD is released after t
VDRELEASE
temporization when lower threshold is crossed, HVD is asserted t
VDASSERT
after
detection when upper threshold is crossed. HVD140 does not cause reset.
9
This supply also needs to be below 5472 mV (untrimmed HVD600 min)
10
The PMC supply also needs to be below 5472 mV (untrimmed HVD600 mV).
11
Untrimmed LVD300_A will be asserted first on power down.
12
Hysteresis is implemented only between the VDD_HV_IO_MAIN High voltage Supplies and the ADC high voltage
supply. When these two supplies are shorted together, the hysteresis is as is shown in Table 37. If the supplies are not
shorted (VDD_IO_MAIN and ADC high voltage supply), then there will be no hysteresis on the high voltage supplies.
13
V
DD_HV_FLA
supply range is guaranteed by internal regulator.
Table 38. Device supply relation during power-up/power-down sequence
Supply 2
1
1
Red cells: supply1 (row) can exceed supply2 (column), granted that external circuitry ensure current flowing from supply1
is less than absolute maximum rating current value provided.
V
DD_LV
V
DD_HV_PMC
V
DD_HV_IO
V
DD_HV_FLA
V
DD_HV_ADV
V
DD_HV_ADR
ALTREFn
2
2
ALTREFn are the alternate references for the ADC that can be used in place of the default reference (V
DD_HV_ADR_*
). They
are SARB.ALTREF and SAR2.ALTREF.
V
DDSTBY
Supply 1
1
V
DD_LV
V
DD_HV_PMU
V
DD_HV_IO
V
DD_HV_FLA
2mA
3
3
V
DD_HV_FLA
is generated internally in normal mode. Above current constraints is guaranteed.
V
DD_HV_ADV
V
DD_HV_ADR
5mA
ALTREFn 10 mA
4
4
ADC performances is not guaranteed with ALTREFn above V
DD_HV_IO
/V
DD_HV_ADV
10 mA
4
V
DDSTBY