NXP Semiconductors MPC5777M - Flash memory AC timing specifications

MPC5777M Microcontroller Data Sheet, Rev. 6
Electrical characteristics
NXP Semiconductors84
3.15.6 Flash memory AC timing specifications
3.15.7 Flash read wait state and address pipeline control settings
Table 45 describes the recommended RWSC and APC settings at various operating frequencies based on specified intrinsic
flash access times of the C55FMC array at 150 °C.
Table 44. Flash memory AC timing specifications (characterized but not tested)
Symbol Characteristic Min Typical Max Units
t
psus
Time from setting the MCR-PSUS bit until MCR-DONE bit
is set to a 1.
— 7 plus four
system
clock
periods
9.1 plus
four
system
clock
periods
µs
t
esus
Time from setting the MCR-ESUS bit until MCR-DONE bit
is set to a 1.
— 16 plus
four
system
clock
periods
20.8 plus
four
system
clock
periods
µs
t
res
Time from clearing the MCR-ESUS or PSUS bit with
EHV = 1 until DONE goes low.
——100ns
t
done
Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared.
—— 5ns
t
dones
Time from 1 to 0 transition on the MCR-EHV bit aborting a
program/erase until the MCR-DONE bit is set to a 1.
— 16 plus
four
system
clock
periods
20.8 plus
four
system
clock
periods
µs
t
drcv
Time to recover once exiting low power mode. 16 plus
seven
system
clock
periods
— 45 plus
seven
system
clock
periods
µs
t
aistart
Time from 0 to 1 transition of UT0-AIE initiating a Margin
Read or Array Integrity until the UT0-AID bit is cleared.
This time also applies to the resuming from a suspend or
breakpoint by clearing AISUS or clearing NAIBP
—— 5ns
t
aistop
Time from 1 to 0 transition of UTO-AIE initiating an Array
Integrity abort until the UT0-AID bit is set. This time also
applies to the UT0-AISUS to UT0-AID setting in the event
of a Array Integrity suspend request.
—— 80
plus fifteen
system
clock
periods
ns
t
mrstop
Time from 1 to 0 transition of UTO-AIE initiating a Margin
Read abort until the UT0-AID bit is set. This time also
applies to the UT0-AISUS to UT0-AID setting in the event
of a Margin Read suspend request.
10.36
plus four
system
clock
periods
— 20.42
plus four
system
clock
periods
µs