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General| Core | ARM Cortex-M0 |
|---|---|
| Operating Frequency | 50 MHz |
| I2C | Up to 2 |
| Operating Temperature | -40 °C to +85 °C |
| ADC | 10-bit ADC |
| Communication Interfaces | UART, I2C, SPI |
| USB | USB 2.0 Full-speed Device Controller |
| Package | LQFP48 |
Routine for setting up the system PLL according to calling arguments.
Routine for configuring internal power control settings for active power consumption.
Illustrates the pointer mechanism used to access the on-chip USB driver.
Description of the USB software interface, including endpoint configurations.
Table of supported endpoint configurations and packet sizes.
Description of the RBR register for receiving data.
Description of the THR register for transmitting data.
Registers for setting the baud rate divisor value.
Enables or disables various USART interrupt sources.
Provides a status code for pending interrupts.
Controls the configuration of the USART in RS-485/EIA-485 mode.
Controls serial clock rate, bus type, and data size.
Controls aspects of the SSP/SPI controller operation.
Register for transmitting and receiving data.
Read-only register reflecting the current status of the SPI controller.
Controls setting of bits in the CON register.
Reflects the condition of the I2C interface.
Contains data to be transmitted or received.
Register for clearing and identifying pending interrupts for CT32B0/1.
Controls the operation of the counter/timer.
Registers for the 32-bit Timer Counter.
Controls operations performed when Match Registers match Timer Counter.
Values compared to Timer Counter for triggering actions.
Controls capture function enablement and event detection.
Selects Timer/Counter mode and CAP pin/edge for counting.
Enabling lock features to ensure WWDT operation at all times.
Controls the operation of the Watchdog.
Determines the time-out value for the Watchdog Timer.
Reloads the Watchdog timer with WDTC value and starts the Watchdog.
Reads the current value of the Watchdog timer counter.
Selects the source of the WDT clock.
Determines the counter value that will generate a watchdog interrupt.
Contains control information and provides a status flag.
Specifies the reload value for the SysTick timer.
Returns the current count from the SysTick counter.
Overview of ADC registers and their base addresses.
Register for selecting A/D channels, timing, modes, and start trigger.
Contains the result of the most recent A/D conversion.
