UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 154 of 523
NXP Semiconductors
UM10462
Chapter 9: LPC11U3x/2x/1x GPIO
• Two group interrupts are supported to reflect two distinct interrupt patterns.
• The GPIO group interrupts can wake up the part from sleep, deep-sleep or
power-down modes.
9.3.3 GPIO port features
• GPIO pins can be configured as input or output by software.
• All GPIO pins default to inputs with interrupt disabled at reset.
• Pin registers allow pins to be sensed and set individually.
9.4 Introduction
The GPIO pins can be used in several ways to set pins as inputs or outputs and use the
inputs as combinations of level and edge sensitive interrupts.
9.4.1 GPIO pin interrupts
From all available GPIO pins, up to eight pins can be selected in the system control block
to serve as external interrupt pins (see Table 40
). The external interrupt pins are
connected to eight individual interrupts in the NVIC and are created based on rising or
falling edges or on the input level on the pin.
9.4.2 GPIO group interrupt
For each port/pin connected to one of the two the GPIO Grouped Interrupt blocks
(GROUP0 and GROUP1), the GPIO grouped interrupt registers determine which pins are
enabled to generate interrupts and what the active polarities of each of those inputs are.
The GPIO grouped interrupt registers also select whether the interrupt output will be level
or edge triggered and whether it will be based on the OR or the AND of all of the enabled
inputs.
When the designated pattern is detected on the selected input pins, the GPIO grouped
interrupt block will generate an interrupt. If the part is in a power-savings mode it will first
asynchronously wake the part up prior to asserting the interrupt request. The interrupt
request line can be cleared by writing a one to the interrupt status bit in the control
register.
9.4.3 GPIO port
The GPIO port registers can be used to configure each GPIO pin as input or output and
read the state of each pin if the pin is configured as input or set the state of each pin if the
pin is configured as output.
9.5 Register description
The GPIO consists of the following blocks:
• The GPIO pin interrupts block at address 0x4004 C000. Registers in this block enable
the up to 8 pin interrupts selected in the syscon block PINTSEL registers (see
Table 40
) and configure the level and edge sensitivity for each selected pin interrupt.
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