NXP Semiconductors LPC11U3x User Manual

UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 154 of 523
NXP Semiconductors
UM10462
Chapter 9: LPC11U3x/2x/1x GPIO
• Two group interrupts are supported to reflect two distinct interrupt patterns.
• The GPIO group interrupts can wake up the part from sleep, deep-sleep or
power-down modes.
9.3.3 GPIO port features
• GPIO pins can be configured as input or output by software.
• All GPIO pins default to inputs with interrupt disabled at reset.
• Pin registers allow pins to be sensed and set individually.
9.4 Introduction
The GPIO pins can be used in several ways to set pins as inputs or outputs and use the
inputs as combinations of level and edge sensitive interrupts.
9.4.1 GPIO pin interrupts
From all available GPIO pins, up to eight pins can be selected in the system control block
to serve as external interrupt pins (see Table 40
). The external interrupt pins are
connected to eight individual interrupts in the NVIC and are created based on rising or
falling edges or on the input level on the pin.
9.4.2 GPIO group interrupt
For each port/pin connected to one of the two the GPIO Grouped Interrupt blocks
(GROUP0 and GROUP1), the GPIO grouped interrupt registers determine which pins are
enabled to generate interrupts and what the active polarities of each of those inputs are.
The GPIO grouped interrupt registers also select whether the interrupt output will be level
or edge triggered and whether it will be based on the OR or the AND of all of the enabled
inputs.
When the designated pattern is detected on the selected input pins, the GPIO grouped
interrupt block will generate an interrupt. If the part is in a power-savings mode it will first
asynchronously wake the part up prior to asserting the interrupt request. The interrupt
request line can be cleared by writing a one to the interrupt status bit in the control
register.
9.4.3 GPIO port
The GPIO port registers can be used to configure each GPIO pin as input or output and
read the state of each pin if the pin is configured as input or set the state of each pin if the
pin is configured as output.
9.5 Register description
The GPIO consists of the following blocks:
• The GPIO pin interrupts block at address 0x4004 C000. Registers in this block enable
the up to 8 pin interrupts selected in the syscon block PINTSEL registers (see
Table 40
) and configure the level and edge sensitivity for each selected pin interrupt.

NXP Semiconductors LPC11U3x Specifications

General

Core	ARM Cortex-M0
Operating Frequency	50 MHz
I2C	Up to 2
Operating Temperature	-40 °C to +85 °C
ADC	10-bit ADC
Communication Interfaces	UART, I2C, SPI
USB	USB 2.0 Full-speed Device Controller
Package	LQFP48

Summary

LPC11U3x/2x/1x System Control Block

Clocking and power control

LPC11U3x/2x/1x Power profiles

set_pll

Routine for setting up the system PLL according to calling arguments.

set_power

Routine for configuring internal power control settings for active power consumption.

LPC11U3x/2x/1x USB on-chip drivers

Calling the USB device driver

Illustrates the pointer mechanism used to access the on-chip USB driver.

LPC11U3x/2x/1x USB2.0 device controller

USB software interface

Description of the USB software interface, including endpoint configurations.

Fixed endpoint configuration

Table of supported endpoint configurations and packet sizes.

SoftConnect

Suspend and resume

LPC11U3x/2x/1x USART

USART Receiver Buffer Register (when DLAB = 0, Read Only)

Description of the RBR register for receiving data.

USART Transmitter Holding Register (when DLAB = 0, Write Only)

Description of the THR register for transmitting data.

USART Divisor Latch LSB and MSB Registers (when DLAB = 1)

Registers for setting the baud rate divisor value.

USART Interrupt Enable Register (when DLAB = 0)

Enables or disables various USART interrupt sources.

USART Interrupt Identification Register (Read Only)

Provides a status code for pending interrupts.

USART RS485 Control register

Controls the configuration of the USART in RS-485/EIA-485 mode.

USART Synchronous mode control register

LPC11U3x/2x/1x SSP/SPI

SSP/SPI Control Register 0

Controls serial clock rate, bus type, and data size.

SSP/SPI Control Register 1

Controls aspects of the SSP/SPI controller operation.

SSP/SPI Data Register

Register for transmitting and receiving data.

SSP/SPI Status Register

Read-only register reflecting the current status of the SPI controller.

SSP/SPI Clock Prescale Register

SSP/SPI Interrupt Mask Set/Clear Register

LPC11U3x/2x/1x I2C-bus controller

I2C Control Set register (CONSET)

Controls setting of bits in the CON register.

I2C Status register (STAT)

Reflects the condition of the I2C interface.

I2C Data register (DAT)

Contains data to be transmitted or received.

I2C Slave Address register 0 (ADR0)

I2C SCL HIGH and LOW duty cycle registers (SCLH and SCLL)

I2C Control Clear register (CONCLR)

LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1

Prescale Counter register

LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1

Interrupt Register

Register for clearing and identifying pending interrupts for CT32B0/1.

Timer Control Register

Controls the operation of the counter/timer.

Timer Counter registers

Registers for the 32-bit Timer Counter.

Prescale Register

Prescale Counter Register

Match Control Register

Controls operations performed when Match Registers match Timer Counter.

Match Registers

Values compared to Timer Counter for triggering actions.

Capture Control Register

Controls capture function enablement and event detection.

Count Control Register

Selects Timer/Counter mode and CAP pin/edge for counting.

PWM Control Register

LPC11U3x/2x/1x Windowed Watchdog Timer (WWDT)

Applications

Using the WWDT lock features

Enabling lock features to ensure WWDT operation at all times.

Watchdog mode register

Controls the operation of the Watchdog.

Watchdog Timer Constant register

Determines the time-out value for the Watchdog Timer.

Watchdog Feed register

Reloads the Watchdog timer with WDTC value and starts the Watchdog.

Watchdog Timer Value register

Reads the current value of the Watchdog timer counter.

Watchdog Clock Select register

Selects the source of the WDT clock.

Watchdog Timer Warning Interrupt register

Determines the counter value that will generate a watchdog interrupt.

Watchdog Timer Window register

LPC11U3x/2x/1x System tick timer

System Timer Control and status register

Contains control information and provides a status flag.

System Timer Reload value register

Specifies the reload value for the SysTick timer.

System Timer Current value register

Returns the current count from the SysTick counter.

System Timer Calibration value register

LPC11U3x/2x/1x ADC

Register description

Overview of ADC registers and their base addresses.

A/D Control Register (CR - 0x4001 C000)

Register for selecting A/D channels, timing, modes, and start trigger.

A/D Global Data Register (GDR - 0x4001 C004)

Contains the result of the most recent A/D conversion.

A/D Interrupt Enable Register (INTEN - 0x4001 C00C)

A/D Data Registers (DR0 to DR7 - 0x4001 C010 to 0x4001 C02C)

A/D Status Register (STAT - 0x4001 C030)

LPC11U3x/2x/1x Flash programming firmware

Bootloader

Flash content protection mechanism

Criterion for Valid User Code

ISP/IAP communication protocol

IAP commands

Prepare sector(s) for write operation

Copy RAM to flash

Erase Sector(s)

Blank check sector(s)

Erase page