UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 226 of 523
NXP Semiconductors
UM10462
Chapter 11: LPC11U3x/2x/1x USB2.0 device controller
11.6.1 USB Device Command/Status register (DEVCMDSTAT)
INTSETSTAT R/W 0x028 USB set interrupt status register 0 Table 224
INTROUTING R/W 0x02C USB interrupt routing register 0 Table 225
EPTOGGLE R 0x034 USB Endpoint toggle register 0 Table 226
Table 213. Register overview: USB (base address: 0x4008 0000)
Name Access Address
offset
Description Reset
value
Reference
Table 214. USB Device Command/Status register (DEVCMDSTAT, address 0x4008 0000) bit description
Bit Symbol Value Description Reset
value
Access
6:0 DEV_ADDR USB device address. After bus reset, the address is reset to
0x00. If the enable bit is set, the device will respond on packets
for function address DEV_ADDR. When receiving a SetAddress
Control Request from the USB host, software must program the
new address before completing the status phase of the
SetAddress Control Request.
0RW
7 DEV_EN USB device enable. If this bit is set, the HW will start responding
on packets for function address DEV_ADDR.
0RW
8 SETUP SETUP token received. If a SETUP token is received and
acknowledged by the device, this bit is set. As long as this bit is
set all received IN and OUT tokens will be NAKed by HW. SW
must clear this bit by writing a one. If this bit is zero, HW will
handle the tokens to the CTRL EP0 as indicated by the CTRL
EP0 IN and OUT data information programmed by SW.
0RWC
9 PLL_ON Always PLL Clock on: 0 RW
0 USB_NeedClk functional
1 USB_NeedClk always 1. Clock will not be stopped in case of
suspend.
10 - Reserved. 0 RO
11 LPM_SUP LPM Supported: 1 RW
0 LPM not supported.
1 LPM supported.
12 INTONNAK_AO Interrupt on NAK for interrupt and bulk OUT EP 0 RW
0 Only acknowledged packets generate an interrupt
1 Both acknowledged and NAKed packets generate interrupts.
13 INTONNAK_AI Interrupt on NAK for interrupt and bulk IN EP 0 RW
0 Only acknowledged packets generate an interrupt
1 Both acknowledged and NAKed packets generate interrupts.
14 INTONNAK_CO Interrupt on NAK for control OUT EP 0 RW
0 Only acknowledged packets generate an interrupt
1 Both acknowledged and NAKed packets generate interrupts.
15 INTONNAK_CI Interrupt on NAK for control IN EP 0 RW
0 Only acknowledged packets generate an interrupt
1 Both acknowledged and NAKed packets generate interrupts.
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