UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 36 of 523
NXP Semiconductors
UM10462
Chapter 3: LPC11U3x/2x/1x System control block
3.5.27 CLKOUT clock divider register
This register determines the divider value for the signal on the CLKOUT pin.
3.5.28 POR captured PIO status register 0
The PIOPORCAP0 register captures the state of GPIO port 0 at power-on-reset. Each bit
represents the reset state of one GPIO pin. This register is a read-only status register.
3.5.29 POR captured PIO status register 1
The PIOPORCAP1 register captures the state of GPIO port 1 at power-on-reset. Each bit
represents the reset state of one GPIO pin. This register is a read-only status register.
3.5.30 BOD control register
The BOD control register selects up to four separate threshold values for sending a BOD
interrupt to the NVIC and for forced reset. Reset and interrupt threshold values listed in
Table 36
are typical values.
Table 32. CLKOUT clock source update enable register (CLKOUTUEN, address 0x4004
80E4) bit description
Bit Symbol Value Description Reset value
0 ENA Enable CLKOUT clock source update 0
0 No change
1 Update clock source
31:1 - - Reserved -
Table 33. CLKOUT clock divider registers (CLKOUTDIV, address 0x4004 80E8) bit
description
Bit Symbol Description Reset
value
7:0 DIV CLKOUT clock divider values
0: Disable CLKOUT clock divider.
1: Divide by 1.
to
255: Divide by 255.
0
31:8 - Reserved -
Table 34. POR captured PIO status register 0 (PIOPORCAP0, address 0x4004 8100) bit
description
Bit Symbol Description Reset value
23:0 PIOSTAT State of PIO0_23 through PIO0_0 at power-on reset Implementation
dependent
31:24 - Reserved. -
Table 35. POR captured PIO status register 1 (PIOPORCAP1, address 0x4004 8104) bit
description
Bit Symbol Description Reset value
31:0 PIOSTAT State of PIO1_31 through PIO1_0 at power-on reset Implementation
dependent
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