UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 46 of 523
NXP Semiconductors
UM10462
Chapter 3: LPC11U3x/2x/1x System control block
3.7 Start-up behavior
See Figure 8 for the start-up timing after reset. The IRC is the default clock at Reset and
provides a clean system clock shortly after the supply voltage reaches the threshold value
of 1.8 V.
3.8 Brown-out detection
The LPC11U3x/2x/1x includes up to four levels for monitoring the voltage on the V
DD
pin.
If this voltage falls below one of the selected levels, the BOD asserts an interrupt signal to
the NVIC or issues a reset, depending on the value of the BODRSTENA bit in the BOD
control register (Table 36
).
The interrupt signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC (see Table 436
) in order to cause a CPU interrupt; if not, software can monitor the
signal by reading a dedicated status register.
If the BOD interrupt is enabled in the STARTERP1 register (see Table 44
) and in the
NVIC, the BOD interrupt can wake up the chip from Deep-sleep and power-down mode.
If the BOD reset is enabled, the forced BOD reset can wake up the chip from Deep-sleep
or Power-down mode.
Fig 8. Start-up timing
valid threshold
= 1.8V
processor status
V
DD
IRC status
internal reset
GND
80 μs 101 μs
boot time
user code
boot code
execution
finishes;
user code starts
IRC
starts
supply ramp-up
time
55 μs
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