UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 319 of 523
NXP Semiconductors
UM10462
Chapter 14: LPC11U3x/2x/1x I2C-bus controller
14.10.4 Slave Transmitter mode
In the slave transmitter mode, a number of data bytes are transmitted to a master receiver
(see Figure 52
). Data transfer is initialized as in the slave receiver mode. When ADR and
CON have been initialized, the I
2
C block waits until it is addressed by its own slave
address followed by the data direction bit which must be “1” (R) for the I
2
C block to
operate in the slave transmitter mode. After its own slave address and the R bit have been
received, the serial interrupt flag (SI) is set and a valid status code can be read from STAT.
This status code is used to vector to a state service routine, and the appropriate action to
be taken for each of these status codes is detailed in Table 292
. The slave transmitter
mode may also be entered if arbitration is lost while the I
2
C block is in the master mode
(see state 0xB0).
If the AA bit is reset during a transfer, the I
2
C block will transmit the last byte of the transfer
and enter state 0xC0 or 0xC8. The I
2
C block is switched to the not addressed slave mode
and will ignore the master receiver if it continues the transfer. Thus the master receiver
receives all 1s as serial data. While AA is reset, the I
2
C block does not respond to its own
slave address or a General Call address. However, the I
2
C-bus is still monitored, and
address recognition may be resumed at any time by setting AA. This means that the AA
bit may be used to temporarily isolate the I
2
C block from the I
2
C-bus.
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