UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 279 of 523
NXP Semiconductors
UM10462
Chapter 13: LPC11U3x/2x/1x SSP/SPI
13.6.3 SSP/SPI Data Register
Software can write data to be transmitted to this register and read data that has been
received.
Table 261. SSP/SPI Control Register 1 (CR1 - address 0x4004 0004 (SSP0) and 0x4005 8004
(SSP1)) bit description
Bit Symbol Value Description Reset
Value
0 LBM Loop Back Mode. 0
0 During normal operation.
1 Serial input is taken from the serial output (MOSI or MISO)
rather than the serial input pin (MISO or MOSI
respectively).
1 SSE SPI Enable. 0
0 The SPI controller is disabled.
1 The SPI controller will interact with other devices on the
serial bus. Software should write the appropriate control
information to the other SSP/SPI registers and interrupt
controller registers, before setting this bit.
2 MS Master/Slave Mode.This bit can only be written when the
SSE bit is 0.
0
0 The SPI controller acts as a master on the bus, driving the
SCLK, MOSI, and SSEL lines and receiving the MISO line.
1 The SPI controller acts as a slave on the bus, driving MISO
line and receiving SCLK, MOSI, and SSEL lines.
3 SOD Slave Output Disable. This bit is relevant only in slave
mode (MS = 1). If it is 1, this blocks this SPI controller from
driving the transmit data line (MISO).
0
31:4 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
Table 262. SSP/SPI Data Register (DR - address 0x4004 0008 (SSP0) and 0x4005 8008
(SSP1)) bit description
Bit Symbol Description Reset Value
15:0 DATA Write: software can write data to be sent in a future frame to this
register whenever the TNF bit in the Status register is 1,
indicating that the Tx FIFO is not full. If the Tx FIFO was
previously empty and the SPI controller is not busy on the bus,
transmission of the data will begin immediately. Otherwise the
data written to this register will be sent as soon as all previous
data has been sent (and received). If the data length is less than
16 bit, software must right-justify the data written to this register.
Read: software can read data from this register whenever the
RNE bit in the Status register is 1, indicating that the Rx FIFO is
not empty. When software reads this register, the SPI controller
returns data from the least recent frame in the Rx FIFO. If the
data length is less than 16 bit, the data is right-justified in this
field with higher order bits filled with 0s.
0x0000
31:16 - Reserved. -
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