UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 27 of 523
NXP Semiconductors
UM10462
Chapter 3: LPC11U3x/2x/1x System control block
3.5.9 Internal resonant crystal control register
This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset
and written by the boot code on start-up.
3.5.10 System reset status register
If another reset signal - for example the external RESET pin - remains asserted after the
POR signal is negated, then its bit is set to detected. Write a one to clear the reset.
The reset value given in Table 16
applies to the POR reset.
3.5.11 System PLL clock source select register
This register selects the clock source for the system PLL. The SYSPLLCLKUEN register
(see Section 3.5.12
) must be toggled from LOW to HIGH for the update to take effect.
Table 15. Internal resonant crystal control register (IRCCTRL, address 0x4004 8028) bit
description
Bit Symbol Description Reset value
7:0 TRIM Trim value 0x80 then flash will
reprogram
31:8 - Reserved 0x00
Table 16. System reset status register (SYSRSTSTAT, address 0x4004 8030) bit description
Bit Symbol Value Description Reset
value
0 POR POR reset status 1
0 No POR detected
1 POR detected. Writing a one clears this reset.
1 EXTRST External reset status 1
0 No reset event detected.
1 Reset detected. Writing a one clears this reset.
2 WDT Status of the Watchdog reset 0
0 No WDT reset detected
1 WDT reset detected. Writing a one clears this reset.
3 BOD Status of the Brown-out detect reset 0
0 No BOD reset detected
1 BOD reset detected. Writing a one clears this reset.
4 SYSRST Status of the software system reset 0
0 No System reset detected
1 System reset detected. Writing a one clears this reset.
31:5 - - Reserved -
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