UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 343 of 523
NXP Semiconductors
UM10462
Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1
15.7.10 External Match Register
The External Match Register provides both control and status of the external match pins
CT16Bn_MAT[1:0].
If the match outputs are configured as PWM output, the function of the external match
registers is determined by the PWM rules (Section 15.7.13 “
Rules for single edge
controlled PWM outputs” on page 348).
Table 309: Capture register 1 (CR1, address 0x4001 0030 (CT16B1)) bit description
Bit Symbol Description Reset
value
15:0 CAP Timer counter capture value. 0
31:16 - Reserved. -
Table 310. External Match Register (EMR, address 0x4000 C03C (CT16B0) and 0x4001 003C (CT16B1)) bit
description
Bit Symbol Value Description Reset
value
0 EM0 External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0,
whether or not this output is connected to its pin. When a match occurs between the TC
and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4]
control the functionality of this output. This bit is driven to the
CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON
registers (0 = LOW, 1 = HIGH).
0
1 EM1 External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1,
whether or not this output is connected to its pin. When a match occurs between the TC
and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6]
control the functionality of this output. This bit is driven to the
CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON
registers (0 = LOW, 1 = HIGH).
0
2 EM2 External Match 2. This bit reflects the state of match channel 2. When a match occurs
between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing.
Bits EMR[9:8] control the functionality of this output.
0
3 EM3 External Match 3. This bit reflects the state of output of match channel 3. When a match
occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do
nothing. Bits EMR[11:10] control the functionality of this output.
0
5:4 EMC0 External Match Control 0. Determines the functionality of External Match 0. Table 311
shows the encoding of these bits.
00
0x0 Do Nothing.
0x1 Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is LOW if
pinned out).
0x2 Set the corresponding External Match bit/output to 1 (CT16Bn_MAT0 pin is HIGH if
pinned out).
0x3 Toggle the corresponding External Match bit/output.
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