UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 86 of 523
NXP Semiconductors
UM10462
Chapter 7: LPC11U3x/2x/1x I/O configuration
7.4.1 I/O configuration registers
7.4.1.1 RESET_PIO0_0 register
PIO1_22 R/W 0x0B8 I/O configuration for pin PIO1_22/RI/MOSI1 0x0000 0090 Table 122
PIO1_23 R/W 0x0BC I/O configuration for pin
PIO1_23/CT16B1_MAT1/SSEL1
0x0000 0090 Table 123
PIO1_24 R/W 0x0C0 I/O configuration for pin PIO1_24/
CT32B0_MAT0
0x0000 0090 Table 124
PIO1_25 R/W 0x0C4 I/O configuration for pin
PIO1_25/CT32B0_MAT1
0x0000 0090 Table 125
PIO1_26 R/W 0x0C8 I/O configuration for pin
PIO1_26/CT32B0_MAT2/RXD/IOH_19
0x0000 0090 Table 126
PIO1_27 R/W 0x0CC I/O configuration for pin
PIO1_27/CT32B0_MAT3/TXD/IOH_20
0x0000 0090 Table 127
PIO1_28 R/W 0x0D0 I/O configuration for pin
PIO1_28/CT32B0_CAP0/SCLK
0x0000 0090 Table 128
PIO1_29 R/W 0x0D4 I/O configuration for pin PIO1_29/SCK0/
CT32B0_CAP1
0x0000 0090 Table 129
- R/W 0x0D8 Reserved - -
PIO1_31 R/W 0x0DC I/O configuration for pin PIO1_31 0x0000 0090 Table 130
Table 75. Register overview: I/O configuration (base address 0x4004 4000) …continued
Name Access Address
offset
Description Reset value Reference
Table 76. RESET_PIO0_0 register (RESET_PIO0_0, address 0x4004 4000) bit
description
Bit Symbol Value Description Reset
value
2:0 FUNC Selects pin function. Values 0x2 to 0x7 are reserved. 000
0x0 RESET
.
0x1 PIO0_0.
4:3 MODE Selects function mode (on-chip pull-up/pull-down resistor
control).
10
0x0 Inactive (no pull-down/pull-up resistor enabled).
0x1 Pull-down resistor enabled.
0x2 Pull-up resistor enabled.
0x3 Repeater mode.
5 HYS Hysteresis. 0
0 Disable.
1 Enable.
6 INV Invert input 0
0 Input not inverted (HIGH on pin reads as 1, LOW on pin reads
as 0).
1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as
1).
9:7 - - Reserved. 001
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