UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 160 of 523
NXP Semiconductors
UM10462
Chapter 9: LPC11U3x/2x/1x GPIO
9.5.1.8 Pin interrupt rising edge register
This register contains ones for pin interrupts selected in the PINTSELn registers (see
Table 40
) on which a rising edge has been detected. Writing ones to this register clears
rising edge detection. Ones in this register assert an interrupt request for pins that are
enabled for rising-edge interrupts. All edges are detected for all pins selected by the
PINTSELn registers, regardless of whether they are interrupt-enabled.
9.5.1.9 Pin interrupt falling edge register
This register contains ones for pin interrupts selected in the PINTSELn registers (see
Table 40
) on which a falling edge has been detected. Writing ones to this register clears
falling edge detection. Ones in this register assert an interrupt request for pins that are
enabled for falling-edge interrupts. All edges are detected for all pins selected by the
PINTSELn registers, regardless of whether they are interrupt-enabled.
Table 147. Pin interrupt active level (falling edge) interrupt clear register (CIENF, address
0x4004 C018) bit description
Bit Symbol Description Reset
value
Access
7:0 CENAF Ones written to this address clears bits in the IENF, thus
disabling interrupts. Bit n clears bit n in the IENF register.
0 = No operation.
1 = LOW-active interrupt selected or falling edge interrupt
disabled.
NA WO
31:8 - Reserved. - -
Table 148. Pin interrupt rising edge register (RISE, address 0x4004 C01C) bit description
Bit Symbol Description Reset
value
Access
7:0 RDET Rising edge detect. Bit n detects the rising edge of the pin
selected in PINTSELn.
Read 0: No rising edge has been detected on this pin since
Reset or the last time a one was written to this bit.
Write 0: no operation.
Read 1: a rising edge has been detected since Reset or the
last time a one was written to this bit.
Write 1: clear rising edge detection for this pin.
0R/W
31:8 - Reserved. - -
Table 149. Pin interrupt falling edge register (FALL, address 0x4004 C020) bit description
Bit Symbol Description Reset
value
Access
7:0 FDET Falling edge detect. Bit n detects the falling edge of the pin
selected in PINTSELn.
Read 0: No falling edge has been detected on this pin since
Reset or the last time a one was written to this bit.
Write 0: no operation.
Read 1: a falling edge has been detected since Reset or the
last time a one was written to this bit.
Write 1: clear falling edge detection for this pin.
0R/W
31:8 - Reserved. - -
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