UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 161 of 523
NXP Semiconductors
UM10462
Chapter 9: LPC11U3x/2x/1x GPIO
9.5.1.10 Pin interrupt status register
Reading this register returns ones for pin interrupts that are currently requesting an
interrupt. For pins identified as edge-sensitive in the Interrupt Select register, writing ones
to this register clears both rising- and falling-edge detection for the pin. For level-sensitive
pins, writing ones inverts the corresponding bit in the Active level register, thus switching
the active level on the pin.
9.5.2 GPIO GROUP0/GROUP1 interrupt register description
9.5.2.1 Grouped interrupt control register
9.5.2.2 GPIO grouped interrupt port polarity registers
The grouped interrupt port polarity registers determine how the polarity of each enabled
pin contributes to the grouped interrupt. Each port is associated with its own port polarity
register, and the values of both registers together determine the grouped interrupt.
Table 150. Pin interrupt status register (IST address 0x4004 C024) bit description
Bit Symbol Description Reset
value
Access
7:0 PSTAT Pin interrupt status. Bit n returns the status, clears the edge
interrupt, or inverts the active level of the pin selected in
PINTSELn.
Read 0: interrupt is not being requested for this interrupt pin.
Write 0: no operation.
Read 1: interrupt is being requested for this interrupt pin.
Write 1 (edge-sensitive): clear rising- and falling-edge
detection for this pin.
Write 1 (level-sensitive): switch the active level for this pin (in
the IENF register).
0R/W
31:8 - Reserved. - -
Table 151. GPIO grouped interrupt control register (CTRL, addresses 0x4005 C000 (GROUP0
INT) and 0x4006 0000 (GROUP1 INT)) bit description
Bit Symbol Value Description Reset value
0 INT Group interrupt status. This bit is cleared by writing a
one to it. Writing zero has no effect.
0
0 No interrupt request is pending.
1 Interrupt request is active.
1 COMB Combine enabled inputs for group interrupt 0
0 OR functionality: A grouped interrupt is generated
when any one of the enabled inputs is active (based
on its programmed polarity).
1 AND functionality: An interrupt is generated when all
enabled bits are active (based on their programmed
polarity).
2 TRIG Group interrupt trigger 0
0 Edge-triggered
1 Level-triggered
31:3 - - Reserved 0
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