UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 61 of 523
NXP Semiconductors
UM10462
Chapter 5: LPC11U3x/2x/1x Power profiles
5.5 Definitions
The following elements have to be defined in an application that uses the power profiles:
typedef struct _PWRD {
void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
void (*set_power)(unsigned int cmd[], unsigned int resp[]);
} PWRD;
#define rom_driver_ptr (*(ROM) **) 0x1FFF 1FF8)
pPWRD = (PWRD *)(rom_driver_ptr->pPWRD);
5.6 Clocking routine
5.6.1 set_pll
This routine sets up the system PLL according to the calling arguments. If the expected
clock can be obtained by simply dividing the system PLL input, set_pll bypasses the PLL
to lower system power consumption.
Remark: Before this routine is invoked, the PLL clock source (IRC/system oscillator) must
be selected (Table 17
), the main clock source must be set to the input clock to the system
PLL (Table 19
) and the system/AHB clock divider must be set to 1 (Table 21).
set_pll attempts to find a PLL setup that matches the calling parameters. Once a
combination of a feedback divider value (SYSPLLCTRL, M), a post divider ratio
(SYSPLLCTRL, P) and the system/AHB clock divider (SYSAHBCLKDIV) is found, set_pll
applies the selected values and switches the main clock source selection to the system
PLL clock out (if necessary).
The routine returns a result code that indicates if the system PLL was successfully set
(PLL_CMD_SUCCESS) or not (in which case the result code identifies what went wrong).
The current system frequency value is also returned. The application should use this
information to adjust other clocks in the device (the SSP, UART, and WDT clocks, and/or
clockout).
The following definitions are needed when making set_pll power routine calls:
/* set_pll mode options */
#define CPU_FREQ_EQU 0
#define CPU_FREQ_LTE 1
Table 57. set_pll routine
Routine set_pll
Input Param0: system PLL input frequency (in kHz)
Param1: expected system clock (in kHz)
Param2: mode (CPU_FREQ_EQU, CPU_FREQ_LTE, CPU_FREQ_GTE,
CPU_FREQ_APPROX)
Param3: system PLL lock time-out
Result Result0: PLL_CMD_SUCCESS | PLL_INVALID_FREQ | PLL_INVALID_MODE |
PLL_FREQ_NOT_FOUND | PLL_NOT_LOCKED
Result1: system clock (in kHz)
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