NXP Semiconductors LPC11U3x User Manual

UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 25 of 523
NXP Semiconductors
UM10462
Chapter 3: LPC11U3x/2x/1x System control block
3.5.6 USB PLL status register
This register is a Read-only register and supplies the PLL lock status (see
Section 3.10.1
).
3.5.7 System oscillator control register
This register configures the frequency range for the system oscillator.
Table 11. USB PLL control register (USBPLLCTRL, address 0x4004 8010) bit
description
Bit Symbol Value Description Reset
value
4:0 MSEL Feedback divider value. The division value M is the
programmed MSEL value + 1.
00000: Division ratio M = 1
to
11111: Division ratio M = 32
0x000
6:5 PSEL Post divider ratio P. The division ratio is 2  P. 0x00
0x0 P = 1
0x1 P = 2
0x2 P = 4
0x3 P = 8
31:7 - - Reserved. Do not write ones to reserved bits. 0x00
Table 12. USB PLL status register (USBPLLSTAT, address 0x4004 8014) bit description
Bit Symbol Value Description Reset
value
0 LOCK PLL lock status 0x0
0 PLL not locked
1 PLL locked
31:1 - - Reserved 0x00
Table 13. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit
description
Bit Symbol Value Description Reset
value
0 BYPASS Bypass system oscillator 0x0
0 Oscillator is not bypassed.
1 Bypass enabled. PLL input (sys_osc_clk) is fed
directly from the XTALIN pin bypassing the
oscillator. Use this mode when using an external
clock source instead of the crystal oscillator.
1 FREQRANGE Determines frequency range for Low-power
oscillator.
0x0
0 1 - 20 MHz frequency range.
1 15 - 25 MHz frequency range
31:2 - - Reserved 0x00

NXP Semiconductors LPC11U3x Specifications

General

Brand	NXP Semiconductors
Model	LPC11U3x
Category	Microcontrollers
Language	English