UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 358 of 523
NXP Semiconductors
UM10462
Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1
16.7.7 Match Registers
The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.
16.7.8 Capture Control Register
The Capture Control Register is used to control whether one of the four Capture Registers
is loaded with the value in the Timer Counter when the capture event occurs, and whether
an interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, “n” represents the Timer number, 0 or 1.
Remark: The bit positions for the CAP1 channel control bits are different for
counter/timers CT32B0 (bits 8:6, Table 326
) and CT32B1 (bits 5:3, Table 327).
11 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches
the TC.
0
1 Enabled
0 Disabled
31:12 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 324: Match Control Register (MCR, address 0x4001 4014 (CT32B0) and 0x4001 8014 (CT32B1)) bit description
Bit Symbol Value Description Reset
value
Table 325: Match registers (MR[0:3], addresses 0x4001 4018 (MR0) to 0x4001 4024 (MR3)
(CT32B0) and 0x4001 8018(MR0) to 0x40018024 (MR3) (CT32B1)) bit description
Bit Symbol Description Reset
value
31:0 MATCH Timer counter match value. 0
Table 326: Capture Control Register (CCR, address 0x4001 4028 (CT32B0) ) bit description
Bit Symbol Value Description Reset
value
0 CAP0RE Capture on CT32B0_CAP0 rising edge: a sequence of 0 then 1 on CT32B0_CAP0 will
cause CR0 to be loaded with the contents of TC.
0
1 Enabled.
0 Disabled.
1 CAP0FE Capture on CT32B0_CAP0 falling edge: a sequence of 1 then 0 on CT32B0_CAP0 will
cause CR0 to be loaded with the contents of TC.
0
1 Enabled.
0 Disabled.
2 CAP0I Interrupt on CT32B0_CAP0 event: a CR0 load due to a CT32B0_CAP0 event will
generate an interrupt.
0
1 Enabled.
0 Disabled.
5:3 - Reserved. -
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