UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 280 of 523
NXP Semiconductors
UM10462
Chapter 13: LPC11U3x/2x/1x SSP/SPI
13.6.4 SSP/SPI Status Register
This read-only register reflects the current status of the SPI controller.
13.6.5 SSP/SPI Clock Prescale Register
This register controls the factor by which the Prescaler divides the SPI peripheral clock
SPI_PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in the
SSPCR0 registers, to determine the bit clock.
Important: the SSPnCPSR value must be properly initialized, or the SPI controller will not
be able to transmit data correctly.
In Slave mode, the SPI clock rate provided by the master must not exceed 1/12 of the SPI
peripheral clock selected in Table 25
. The content of the SSPnCPSR register is not
relevant.
In master mode, CPSDVSR
min
= 2 or larger (even numbers only).
13.6.6 SSP/SPI Interrupt Mask Set/Clear Register
This register controls whether each of the four possible interrupt conditions in the SPI
controller are enabled.
Table 263. SSP/SPI Status Register (SR - address 0x4004 000C (SSP0) and 0x4005 800C
(SSP1)) bit description
Bit Symbol Description Reset Value
0 TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is
empty, 0 if not.
1
1 TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1
2 RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is
empty, 1 if not.
0
3 RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if
not.
0
4 BSY Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently
sending/receiving a frame and/or the Tx FIFO is not empty.
0
31:5 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA
Table 264. SSP/SPI Clock Prescale Register (CPSR - address 0x4004 0010 (SSP0) and
0x4005 8010 (SSP1)) bit description
Bit Symbol Description Reset Value
7:0 CPSDVSR This even value between 2 and 254, by which SPI_PCLK is
divided to yield the prescaler output clock. Bit 0 always reads
as 0.
0
31:8 - Reserved. -
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