UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 276 of 523
NXP Semiconductors
UM10462
Chapter 13: LPC11U3x/2x/1x SSP/SPI
13.5 Pin description
13.6 Register description
The register addresses of the SPI controllers are shown in Table 258.
The reset value reflects the data stored in used bits only. It does not include the content of
reserved bits.
Table 257. SSP/SPI pin descriptions
Pin
name
Type
Interface pin
name/function
Pin description
SPI SSI Microwire
SCK0/1 I/O SCK CLK SK Serial Clock. SCK/CLK/SK is a clock signal used
to synchronize the transfer of data. It is driven by
the master and received by the slave. When
SSP/SPI interface is used, the clock is
programmable to be active-high or active-low,
otherwise it is always active-high. SCK only
switches during a data transfer. Any other time, the
SSP/SPI interface either holds it in its inactive state
or does not drive it (leaves it in high-impedance
state).
SSEL0/1 I/O SSEL FS CS Frame Sync/Slave Select. When the SSP/SPI
interface is a bus master, it drives this signal to an
active state before the start of serial data and then
releases it to an inactive state after the data has
been sent.The active state of this signal can be
high or low depending upon the selected bus and
mode. When the SSP/SPI interface is a bus slave,
this signal qualifies the presence of data from the
Master according to the protocol in use.
When there is just one bus master and one bus
slave, the Frame Sync or Slave Select signal from
the Master can be connected directly to the slave’s
corresponding input. When there is more than one
slave on the bus, further qualification of their Frame
Select/Slave Select inputs will typically be
necessary to prevent more than one slave from
responding to a transfer.
MISO0/1 I/O MISO DR(M)
DX(S)
SI(M)
SO(S)
Master In Slave Out. The MISO signal transfers
serial data from the slave to the master. When the
SSP/SPI is a slave, serial data is output on this
signal. When the SSP/SPI is a master, it clocks in
serial data from this signal. When the SSP/SPI is a
slave and is not selected by FS/SSEL, it does not
drive this signal (leaves it in high-impedance state).
MOSI0/1 I/O MOSI DX(M)
DR(S)
SO(M)
SI(S)
Master Out Slave In. The MOSI signal transfers
serial data from the master to the slave. When the
SSP/SPI is a master, it outputs serial data on this
signal. When the SSP/SPI is a slave, it clocks in
serial data from this signal.
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