UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 383 of 523
19.1 How to read this chapter
The ADC block is identical for all LPC11U3x/2x/1x parts.
19.2 Basic configuration
The ADC is configured using the following registers:
1. Pins: The ADC pin functions are configured in the IOCON register block (Section 7.4
).
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 13 (Table 24
).
Power to the ADC is controlled through the PDRUNCFG register (Table 47
).
Remark: Basic clocking for the A/D converters is determined by the APB clock (PCLK). A
programmable divider is included in the A/D converter to scale this clock to the 4.5 MHz
(max) clock needed by the successive approximation process. An accurate conversion
requires 11 clock cycles.
19.3 Features
• 10-bit successive approximation Analog-to-Digital Converter (ADC).
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range 0 to 3.6 V. Do not exceed the V
DD
voltage level.
• 10-bit conversion time 2.44 s.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on input pin or Timer Match signal.
• Individual result registers for each A/D channel to reduce interrupt overhead.
19.4 Pin description
Table 350 gives a brief summary of the ADC related pins.
UM10462
Chapter 19: LPC11U3x/2x/1x ADC
Rev. 5.5 — 21 December 2016 User manual
Table 350. ADC pin description
Pin Type Description
AD[7:0] Input Analog Inputs. The A/D converter cell can measure the voltage on any
of these input signals.
Remark: While the pins are 5 V tolerant in digital mode, the maximum
input voltage must not exceed V
DD
when the pins are configured as
analog inputs.
V
DD
Input V
REF
; Reference voltage.
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