UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 360 of 523
NXP Semiconductors
UM10462
Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1
16.7.9 Capture Registers
Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
Remark: The location of the CR1 register relative to the timer base address is different for
CT32B0 (CR1 at +0x034, Table 329
) and CT32B1 (CR1 at +0x030, Table 319).
16.7.10 External Match Register
The External Match Register provides both control and status of the external match pins
CAP32Bn_MAT[3:0].
If the match outputs are configured as PWM output, the function of the external match
registers is determined by the PWM rules (Section 16.7.13 “
Rules for single edge
controlled PWM outputs” on page 365).
5 CAP1I Interrupt on CT32B1_CAP1 event: a CR1 load due to a CT32B1_CAP1 event will
generate an interrupt.
0
1 Enabled.
0 Disabled.
31:6 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 327: Capture Control Register (CCR, address 0x4001 8028 (CT32B1)) bit description
Bit Symbol Value Description Reset
value
Table 328: Capture registers (CR0, addresses 0x4001 402C(CT32B0) and 0x4001 802C
(CT32B1)) bit description
Bit Symbol Description Reset
value
31:0 CAP Timer counter capture value. 0
Table 329: Capture register (CR1, address 0x4001 4034 (CT32B0)) bit description
Bit Symbol Description Reset
value
31:0 CAP Timer counter capture value. 0
Table 330: Capture register (CR1, address 0x4001 8030 (CT32B1)) bit description
Bit Symbol Description Reset
value
31:0 CAP Timer counter capture value. 0