UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 361 of 523
NXP Semiconductors
UM10462
Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1
Table 331: External Match Register (EMR, address 0x4001 403C (CT32B0) and 0x4001 803C (CT32B1)) bit
description
Bit Symbol Value Description Reset
value
0 EM0 External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this
output is connected to its pin. When a match occurs between the TC and MR0, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the
functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if
the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0
1 EM1 External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this
output is connected to its pin. When a match occurs between the TC and MR1, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the
functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if
the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0
2 EM2 External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this
output is connected to its pin. When a match occurs between the TC and MR2, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the
functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if
the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0
3 EM3 External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this
output is connected to its pin. When a match occurs between the TC and MR3, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the
functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT3 pins if
the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
0
5:4 EMC0 External Match Control 0. Determines the functionality of External Match 0. 00
0x0 Do Nothing.
0x1 Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if
pinned out).
0x2 Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if
pinned out).
0x3 Toggle the corresponding External Match bit/output.
7:6 EMC1 External Match Control 1. Determines the functionality of External Match 1. 00
0x0 Do Nothing.
0x1 Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT1 pin is LOW if
pinned out).
0x2 Set the corresponding External Match bit/output to 1 (CT32Bi_MAT1 pin is HIGH if
pinned out).
0x3 Toggle the corresponding External Match bit/output.
9:8 EMC2 External Match Control 2. Determines the functionality of External Match 2. 00
0x0 Do Nothing.
0x1 Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT2 pin is LOW if
pinned out).
0x2 Set the corresponding External Match bit/output to 1 (CT32Bi_MAT2 pin is HIGH if
pinned out).
0x3 Toggle the corresponding External Match bit/output.
To Next Page
Loading...
