UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 68 of 523
6.1 How to read this chapter
The NVIC is identical for all LPC11U3x/2x/1x parts. See Section 24.5.2 for details.
Interrupt 31 (I/O Handler interrupt) is available on part LPC11U37HFBD64/401 only.
6.2 Introduction
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
6.3 Features
• Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0
• Tightly coupled interrupt controller provides low interrupt latency
• Controls system exceptions and peripheral interrupts
• The NVIC supports 32 vectored interrupts
• 4 programmable interrupt priority levels with hardware priority level masking
• Software interrupt generation
• Support for NMI
6.4 Interrupt sources
Table 59 lists the interrupt sources for each peripheral function. Each peripheral device
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source. There is no significance or priority about what
line is connected where, except for certain standards from ARM.
See Section 24.5.2
for the NVIC register bit descriptions.
UM10462
Chapter 6: LPC11U3x/2x/1x NVIC
Rev. 5.5 — 21 December 2016 User manual
Table 59. Connection of interrupt sources to the Vectored Interrupt Controller
Interrupt
number
Name Description Flags
0 PIN_INT0 GPIO pin interrupt 0 -
1 PIN_INT1 GPIO pin interrupt 1 -
2 PIN_INT2 GPIO pin interrupt 2 -
3 PIN_INT3 GPIO pin interrupt 3 -
4 PIN_INT4 GPIO pin interrupt 4 -
5 PIN_INT5 GPIO pin interrupt 5 -
6 PIN_INT6 GPIO pin interrupt 6 -
7 PIN_INT7 GPIO pin interrupt 7 -
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