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User manual Rev. 5.5 — 21 December 2016 342 of 523
NXP Semiconductors
UM10462
Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1
15.7.9 Capture Registers
Each Capture register is associated with a device pin and may be loaded with the
counter/timer value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
Remark: The location of the CR1 register relative to the timer base address is different for
CT16B0 (CR1 at +0x034, Table 308
) and CT16B1 (CR1 at +0x030, Table 309).
2 CAP0I Interrupt on CT16B1_CAP0 event: a CR0 load due to a CT16B1_CAP0 event will
generate an interrupt.
0
1 Enabled.
0 Disabled.
3 CAP1RE Capture on CT16B1_CAP1 rising edge: a sequence of 0 then 1 on CT16B1_CAP1 will
cause CR1 to be loaded with the contents of TC.
0
1 Enabled.
0 Disabled.
4 CAP1FE Capture on CT16B1_CAP1 falling edge: a sequence of 1 then 0 on CT16B1_CAP1 will
cause CR1 to be loaded with the contents of TC.
0
1 Enabled.
0 Disabled.
5 CAP1I Interrupt on CT16B1_CAP1 event: a CR1 load due to a CT16B0_CAP1 event will
generate an interrupt.
0
1 Enabled.
0 Disabled.
31:6 - - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 306. Capture Control Register (CCR, address 0x4001 0028 (CT16B1)) bit description
Bit Symbol Value Description Reset
value
Table 307: Capture register 0 (CR0, address 0x4000 C02C (CT16B0) and address 0x4001
002C (CT16B1)) bit description
Bit Symbol Description Reset
value
15:0 CAP Timer counter capture value. 0
31:16 - Reserved. -
Table 308: Capture register 1 (CR1, address 0x4000 C034 (CT16B0)) bit description
Bit Symbol Description Reset
value
15:0 CAP Timer counter capture value. 0
31:16 - Reserved. -