UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 281 of 523
NXP Semiconductors
UM10462
Chapter 13: LPC11U3x/2x/1x SSP/SPI
13.6.7 SSP/SPI Raw Interrupt Status Register
This read-only register contains a 1 for each interrupt condition that is asserted,
regardless of whether or not the interrupt is enabled in the IMSC registers.
13.6.8 SSP/SPI Masked Interrupt Status Register
This read-only register contains a 1 for each interrupt condition that is asserted and
enabled in the IMSC registers. When an SSP/SPI interrupt occurs, the interrupt service
routine should read this register to determine the causes of the interrupt.
Table 265. SSP/SPI Interrupt Mask Set/Clear register (IMSC - address 0x4004 0014 (SSP0)
and 0x4005 8014 (SSP1)) bit description
Bit Symbol Description Reset
Value
0 RORIM Software should set this bit to enable interrupt when a Receive
Overrun occurs, that is, when the Rx FIFO is full and another frame is
completely received. The ARM spec implies that the preceding frame
data is overwritten by the new frame data when this occurs.
0
1 RTIM Software should set this bit to enable interrupt when a Receive
Time-out condition occurs. A Receive Time-out occurs when the Rx
FIFO is not empty, and no has not been read for a time-out period.
The time-out period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR ï‚´
[SCR+1]).
0
2 RXIM Software should set this bit to enable interrupt when the Rx FIFO is at
least half full.
0
3 TXIM Software should set this bit to enable interrupt when the Tx FIFO is at
least half empty.
0
31:4 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
Table 266. SSP/SPI Raw Interrupt Status register (RIS - address 0x4004 0018 (SSP0) and
0x4005 8018 (SSP1)) bit description
Symbol Description Reset
value
0 RORRIS This bit is 1 if another frame was completely received while the
RxFIFO was full. The ARM spec implies that the preceding frame
data is overwritten by the new frame data when this occurs.
0
1 RTRIS This bit is 1 if the Rx FIFO is not empty, and has not been read for a
time-out period. The time-out period is the same for master and slave
modes and is determined by the SSP bit rate: 32 bits at PCLK /
(CPSDVSR ï‚´ [SCR+1]).
0
2 RXRIS This bit is 1 if the Rx FIFO is at least half full. 0
3 TXRIS This bit is 1 if the Tx FIFO is at least half empty. 1
31:4 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
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