NXP Semiconductors LPC11U3x User Manual

UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 33 of 523
NXP Semiconductors
UM10462
Chapter 3: LPC11U3x/2x/1x System control block
3.5.19 SSP0 clock divider register
This register configures the SSP0 peripheral clock SPI0_PCLK. SPI0_PCLK can be shut
down by setting the DIV field to zero.
3.5.20 USART clock divider register
This register configures the USART peripheral clock UART_PCLK. The UART_PCLK can
be shut down by setting the DIV field to zero.
24 GROUP1INT Enables clock to GPIO GROUP1 interrupt register
interface.
0
0 Disable
1 Enable
25 - - Reserved -
26 RAM1 Enables SRAM1 block at address 0x2000 0000. See
Section 3.1
for availability of this bit.
0
0 Disable
1 Enable
27 USBRAM Enables USB SRAM block at address 0x2000 4000. 0
0 Disable
1 Enable
31:28 - - Reserved -
Table 24. System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description
…continued
Bit Symbol Value Description Reset
value
Table 25. SSP0 clock divider register (SSP0CLKDIV, address 0x4004 8094) bit description
Bit Symbol Description Reset
value
7:0 DIV SPI0_PCLK clock divider values.
0: System clock disabled.
1: Divide by 1.
to
255: Divide by 255.
0
31:8 - Reserved -
Table 26. USART clock divider register (UARTCLKDIV, address 0x4004 8098) bit description
Bit Symbol Description Reset
value
7:0 DIV UART_PCLK clock divider values
0: Disable UART_PCLK.
1: Divide by 1.
to
255: Divide by 255.
0
31:8 - Reserved -

NXP Semiconductors LPC11U3x Specifications

General

Brand	NXP Semiconductors
Model	LPC11U3x
Category	Microcontrollers
Language	English