UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 300 of 523
NXP Semiconductors
UM10462
Chapter 14: LPC11U3x/2x/1x I2C-bus controller
14.7.10 I
2
C Mask registers (MASK[0, 1, 2, 3])
The four mask registers each contain seven active bits (7:1). Any bit in these registers
which is set to ‘1’ will cause an automatic compare on the corresponding bit of the
received address when it is compared to the ADRn register associated with that mask
register. In other words, bits in an ADRn register which are masked are not taken into
account in determining an address match.
On reset, all mask register bits are cleared to ‘0’.
The mask register has no effect on comparison to the General Call address (“0000000”).
Bits(31:8) and bit(0) of the mask registers are unused and should not be written to. These
bits will always read back as zeros.
When an address-match interrupt occurs, the processor will have to read the data register
(DAT) to determine what the received address was that actually caused the match.
14.8 Functional description
Figure 41 shows how the on-chip I
2
C-bus interface is implemented, and the following text
describes the individual blocks.
Table 281. I
2
C Data buffer register (DATA_BUFFER - 0x4000 002C) bit description
Bit Symbol Description Reset value
7:0 Data This register holds contents of the 8 MSBs of the DAT shift
register.
0
31:8 - Reserved. The value read from a reserved bit is not defined. 0
Table 282. I
2
C Mask registers (MASK[0, 1, 2, 3] - 0x4000 00[30, 34, 38, 3C]) bit description
Bit Symbol Description Reset value
0 - Reserved. User software should not write ones to reserved
bits. This bit reads always back as 0.
0
7:1 MASK Mask bits. 0x00
31:8 - Reserved. The value read from reserved bits is undefined. 0
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