UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 73 of 523
NXP Semiconductors
UM10462
Chapter 6: LPC11U3x/2x/1x NVIC
6.5.3 Interrupt Set Pending Register 0 register
The ISPR0 register allows setting the pending state of the peripheral interrupts, or for
reading the pending state of those interrupts. Clear the pending state of interrupts through
the ICPR0 registers (Section 6.5.4
).
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 changes the interrupt state to pending.
Read — 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is
pending.
20 ICE_SSP0 Interrupt disable. 0
21 ICE_USART0 Interrupt disable. 0
22 ICE_USB_IRQ Interrupt disable. 0
23 ICE_USB_FIQ Interrupt disable. 0
24 ICE_ADC0 Interrupt disable. 0
25 ICE_WWDT Interrupt disable. 0
26 ICE_BOD Interrupt disable. 0
27 ICE_FLASH Interrupt disable. 0
28 - Reserved. 0
29 - Reserved. 0
30 ICE_USB_WAKEKUP Interrupt disable. 0
31 ICE_IOH Interrupt disable. 0
Table 62. Interrupt clear enable register 0 (ICER0, address 0xE000 E180)
…continued
Bit Symbol Description Reset value
Table 63. Interrupt set pending register 0 register (ISPR0, address 0xE000 E200) bit
description
Bit Symbol Description Reset value
0 ISP_PININT0 Interrupt pending set. 0
1 ISP_PININT1 Interrupt pending set. 0
2 ISP_PININT2 Interrupt pending set. 0
3 ISP_PININT3 Interrupt pending set. 0
4 ISP_PININT4 Interrupt pending set. 0
5 ISP_PININT5 Interrupt pending set. 0
6 ISP_PININT6 Interrupt pending set. 0
7 ISP_PININT7 Interrupt pending set. 0
8 ISP_GINT0 Interrupt pending set. 0
9 ISP_GINT1 Interrupt pending set. 0
10 - Reserved. 0
11 - Reserved. 0
12 - Reserved. 0
13 - Reserved. 0
14 ISP_SSP1 Interrupt pending set. 0
15 ISP_I2C0 Interrupt pending set. 0
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