UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 277 of 523
NXP Semiconductors
UM10462
Chapter 13: LPC11U3x/2x/1x SSP/SPI
Remark: Register names use the SSP prefix to indicate that the SPI controllers have full
SSP capabilities.
13.6.1 SSP/SPI Control Register 0
This register controls the basic operation of the SSP/SPI controller.
Table 258. Register overview: SSP/SPI0 (base address 0x4004 0000)
Name Access Address
offset
Description Reset
value
Reference
CR0 R/W 0x000 Control Register 0. Selects the serial clock rate, bus type,
and data size.
0 Table 260
CR1 R/W 0x004 Control Register 1. Selects master/slave and other
modes.
0 Table 261
DR R/W 0x008 Data Register. Writes fill the transmit FIFO, and reads
empty the receive FIFO.
0 Table 262
SR RO 0x00C Status Register 0x0000
0003
Table 263
CPSR R/W 0x010 Clock Prescale Register 0 Table 264
IMSC R/W 0x014 Interrupt Mask Set and Clear Register 0 Table 265
RIS RO 0x018 Raw Interrupt Status Register 0x0000
0008
Table 266
MIS RO 0x01C Masked Interrupt Status Register 0 Table 267
ICR WO 0x020 SSPICR Interrupt Clear Register NA Table 268
Table 259. Register overview: SSP/SPI1 (base address 0x4005 8000)
Name Access Address
offset
Description Reset
value
Reference
CR0 R/W 0x000 Control Register 0. Selects the serial clock rate, bus type,
and data size.
0 Table 260
CR1 R/W 0x004 Control Register 1. Selects master/slave and other
modes.
0 Table 261
DR R/W 0x008 Data Register. Writes fill the transmit FIFO, and reads
empty the receive FIFO.
0 Table 262
SR RO 0x00C Status Register 0x0000
0003
Table 263
CPSR R/W 0x010 Clock Prescale Register 0 Table 264
IMSC R/W 0x014 Interrupt Mask Set and Clear Register 0 Table 265
RIS RO 0x018 Raw Interrupt Status Register 0x0000
0008
Table 266
MIS RO 0x01C Masked Interrupt Status Register 0 Table 267
ICR WO 0x020 SSPICR Interrupt Clear Register NA Table 268
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