UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 74 of 523
NXP Semiconductors
UM10462
Chapter 6: LPC11U3x/2x/1x NVIC
6.5.4 Interrupt Clear Pending Register 0 register
The ICPR0 register allows clearing the pending state of the peripheral interrupts, or for
reading the pending state of those interrupts. Set the pending state of interrupts through
the ISPR0 register (Section 6.5.3
).
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read — 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is
pending.
16 ISP_CT16B0 Interrupt pending set. 0
17 ISP_CT16B1 Interrupt pending set. 0
18 ISP_CT32B0 Interrupt pending set. 0
19 ISP_CT32B1 Interrupt pending set. 0
20 ISP_SSP0 Interrupt pending set. 0
21 ISP_USART0 Interrupt pending set. 0
22 ISP_USB_IRQ Interrupt pending set. 0
23 ISP_USB_FIQ Interrupt pending set. 0
24 ISP_ADC Interrupt pending set. 0
25 ISP_WWDT Interrupt pending set. 0
26 ISP_BOD Interrupt pending set. 0
27 ISP_FLASH Interrupt pending set. 0
28 - Reserved. 0
29 - Reserved. 0
30 ISP_USB_WAKEKUP Interrupt pending set. 0
31 ISP_IOH Interrupt pending set. 0
Table 63. Interrupt set pending register 0 register (ISPR0, address 0xE000 E200) bit
description
…continued
Bit Symbol Description Reset value
Table 64. Interrupt clear pending register 0 register (ICPR0, address 0xE000 E280) bit
description
Bit Symbol Function Reset value
0 ICP_PININT0 Interrupt pending clear. 0
1 ICP_PININT1 Interrupt pending clear. 0
2 ICP_PININT2 Interrupt pending clear. 0
3 ICP_PININT3 Interrupt pending clear. 0
4 ICP_PININT4 Interrupt pending clear. 0
5 ICP_PININT5 Interrupt pending clear. 0
6 ICP_PININT6 Interrupt pending clear. 0
7 ICP_PININT7 Interrupt pending clear. 0
8 ICP_GINT0 Interrupt pending clear. 0
9 ICP_GINT1 Interrupt pending clear. 0
10 - Reserved. 0