UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 293 of 523
NXP Semiconductors
UM10462
Chapter 14: LPC11U3x/2x/1x I2C-bus controller
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
14.7.1 I
2
C Control Set register (CONSET)
The CONSET registers control setting of bits in the CON register that controls operation of
the I
2
C interface. Writing a one to a bit of this register causes the corresponding bit in the
I
2
C control register to be set. Writing a zero has no effect.
ADR2 R/W 0x024 I2C Slave Address Register 2. Contains the 7-bit slave
address for operation of the I
2
C interface in slave mode,
and is not used in master mode. The least significant bit
determines whether a slave responds to the General Call
address.
0x00 Table 280
ADR3 R/W 0x028 I2C Slave Address Register 3. Contains the 7-bit slave
address for operation of the I
2
C interface in slave mode,
and is not used in master mode. The least significant bit
determines whether a slave responds to the General Call
address.
0x00 Table 280
DATA_BUFFER RO 0x02C Data buffer register. The contents of the 8 MSBs of the
I2DAT shift register will be transferred to the
DATA_BUFFER automatically after every nine bits (8 bits
of data plus ACK or NACK) has been received on the bus.
0x00 Table 281
MASK0 R/W 0x030 I2C Slave address mask register 0. This mask register is
associated with I2ADR0 to determine an address match.
The mask register has no effect when comparing to the
General Call address (‘0000000’).
0x00 Table 282
MASK1 R/W 0x034 I2C Slave address mask register 1. This mask register is
associated with I2ADR0 to determine an address match.
The mask register has no effect when comparing to the
General Call address (‘0000000’).
0x00 Table 282
MASK2 R/W 0x038 I2C Slave address mask register 2. This mask register is
associated with I2ADR0 to determine an address match.
The mask register has no effect when comparing to the
General Call address (‘0000000’).
0x00 Table 282
MASK3 R/W 0x03C I2C Slave address mask register 3. This mask register is
associated with I2ADR0 to determine an address match.
The mask register has no effect when comparing to the
General Call address (‘0000000’).
0x00 Table 282
Table 270. Register overview: I
2
C (base address 0x4000 0000) …continued
Name Access Address
offset
Description Reset
value
[1]
Reference
Table 271. I
2
C Control Set register (CONSET - address 0x4000 0000) bit description
Bit Symbol Description Reset
value
1:0 - Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
2 AA Assert acknowledge flag.
3SI I
2
C interrupt flag. 0
4 STO STOP flag. 0
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