UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 47 of 523
NXP Semiconductors
UM10462
Chapter 3: LPC11U3x/2x/1x System control block
3.9 Power management
The LPC11U3x/2x/1x support a variety of power control features. In Active mode, when
the chip is running, power and clocks to selected peripherals can be optimized for power
consumption. In addition, there are four special modes of processor power reduction with
different peripherals running: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode.
[1] If bit 5, the clock source lock bit, in the WWDT MOD register is set and the IRC is selected as the WWDT
clock source, the IRC and the IRC output are forced on during this mode (Table 342
). This increases power
consumption and may cause the part not to enter Power-down mode correctly. For details see Section 17.7
.
Remark: The Debug mode is not supported in Sleep, Deep-sleep, Power-down, or Deep
power-down modes.
3.9.1 Reduced power modes and WWDT lock features
The WWDT clock select lock feature influences the power consumption in any of the
power modes because locking the WWDT clock source forces the selected WWDT clock
source to be on independently of the Deep-sleep and Power-down mode software
configuration through the PDSLEEPCFG register. For details see Section 17.7
.
If the part uses Deep-sleep mode with the WWDT running, the watchdog oscillator is the
preferred clock source as it minimizes power consumption. If the clock source is not
locked, the watchdog oscillator must be powered by using the PDSLEEPCFG register.
Alternatively, the IRC may be selected and locked in WWDT MOD register, which forces
the IRC on during Deep-sleep mode.
If the part uses Power-down mode with the WWDT running, the watchdog oscillator must
be selected as the clock source. If the clock source is not locked, the watchdog oscillator
must be powered by using the PDSLEEPCFG register. Do not lock the clock source with
the IRC selected.
Table 50. Peripheral configuration in reduced power modes
Peripheral Sleep mode Deep-sleep
mode
Power-down
mode
Deep power-down
mode
IRC software configurable on off
[1]
off
IRC output software configurable off
[1]
off
[1]
off
Flash software configurable on off off
BOD software configurable software
configurable
software
configurable
off
PLL software configurable off off off
SysOsc software configurable off off off
WDosc/WWDT software configurable software
configurable
software
configurable
off
ADC software configurable off off off
Digital peripherals software configurable off off off
USB software configurable off off off
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